IP Library Granted Patent US 7,251,165
Granted Patent B2
US 7,251,165 · App. 10/930,873 · Granted Jul 31, 2007

Semiconductor flash memory

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,251,165
App. No.
10/930,873
Granted
Jul 31, 2007
Kind
B2
Abstract

A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.

Claims (8)

1. A semiconductor flash memory comprising:

an erase/write control unit that,

when performing an erase/write operation of a plurality of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and,

when performing a verify operation, carries out a verify read for each one of the memory cells in which the same data is stored, individually; and

a readout control unit that,

when performing a read operation, selects at least two read memory cells from among the read memory cells in which the erase/write control unit stores the same data, and senses total memory current for the at least two read memory cells, and,

when performing the verify operation, carries out a verify read for each of the memory cells, individually.

2. The semiconductor flash memory according to claim 1 , wherein the erase/write control unit adjusts the threshold voltage of the at least two read memory cells so that a difference between a word line voltage that sets a write threshold lower limit and a read word line voltage is larger than a difference between a word line voltage that sets an erase threshold lower limit and an unselected word line voltage.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Sep 8, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024953/0211 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2004
From: TAITO, YASUHIKO; OTANI, NAOKI; OMOTO, KAYOKO; KODA, KENJI
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 015757/0600 →