Precision adaptive equalizer
View Patent ↗In accordance with the teachings described herein, systems and methods are provided for a precision adaptive equalizer. A variable gain equalizer may be used to apply a variable gain to an input signal to generate an equalized output signal. A phase and pattern detector circuit may be coupled in a feedback loop with the variable gain equalizer. The phase and pattern detector circuit may be used to identify a high frequency data pattern in the equalized output signal and compare the high frequency data pattern with a clock signal to detect a high frequency phase error. The phase and pattern detector circuit may be further operable to generate an automatic gain control signal as a function of the high frequency phase error, the automatic gain control signal being fed back to the variable gain equalizer to control the variable gain applied to the input signal.
1. A precision adaptive equalizer circuit, comprising:
a variable gain equalizer operable to apply a variable gain to an input signal to generate an equalized output signal; and
a phase and pattern detector circuit coupled in a feedback loop with the variable gain equalizer, the phase and pattern detector circuit being operable to identify a high frequency data pattern in the equalized output signal and compare the high frequency data pattern with a clock signal to detect a high frequency phase error;
the phase and pattern detector circuit being further operable to generate a control signal as a function of the high frequency phase error, the control signal being fed back to the variable gain equalizer to control the variable gain applied to the input signal;
a clock and data recovery circuit operable to extract a recovered clock signal from the equalized output signal;
wherein the phase and pattern detector circuit compares the high frequency data pattern with the recovered clock signal to detect the high frequency phase error;
wherein the phase and pattern detector circuit and the clock and data recovery circuit include a common phase detector circuit.
2. The precision adaptive equalizer circuit of claim 1 , wherein the common phase detector circuit is configured in a phase locked loop to form the clock and data recovery circuit.
3. The precision adaptive equalizer circuit of claim 1 , wherein the phase and pattern detector circuit is operable to identify a high frequency data pattern 101 in the equalized output signal.
4. A precision adaptive equalizer circuit, comprising:
a variable gain equalizer operable to apply a variable gain to an input signal to generate an equalized output signal; and
a phase and pattern detector circuit coupled in a feedback loop with the variable gain equalizer, the phase and pattern detector circuit being operable to identify a high frequency data pattern in the equalized output signal and compare the high frequency data pattern with a clock signal to detect a high frequency phase error;
the phase and pattern detector circuit being further operable to generate a control signal as a function of the high frequency phase error, the control signal being fed back to the variable gain equalizer to control the variable gain applied to the input signal;
a clock and data recovery circuit operable to extract a recovered clock signal from the equalized output signal;
wherein the phase and pattern detector circuit compares the high frequency data pattern with the recovered clock signal to detect the high frequency phase error;
wherein the phase and pattern detector circuit is operable to identify a high frequency data pattern 101 in the equalized output signal, the phase and pattern detector comprising:
a first flip-flop that samples the input signal on an edge of the recovered clock signal to generate a first output signal;
a first latch that samples the first output signal on an edge of the recovered clock signal to generate a second output signal;
a second latch that samples the second output signal on an edge of the recovered clock signal to generate a third output signal;
a third latch that samples the third output signal on an edge of the recovered clock signal to generate a forth output signal; and
a second flip-flop that samples the forth output signal on an edge of the first output signal to generate a pattern detector output signal;
wherein the pattern detector output signal indicates when a high frequency data pattern is detected.
5. The precision adaptive equalizer circuit of claim 4 , wherein the phase and pattern detector further comprises:
a phase detector that compares the input signal with the recovered clock signal to generate a phase control signal.
6. The precision adaptive equalizer circuit of claim 5 , wherein the phase and pattern detector further comprises:
an equalizer control signal output latch that samples the phase control signal on an edge of the pattern detector output signal to generate the control signal.
7. The precision adaptive equalizer circuit of claim 1 , further comprising:
an equalizer charge pump coupled between the phase and pattern detector and the variable gain equalizer, the equalizer charge pump being operable to convert the control signal into an analog control signal, wherein the analog control signal is used by the variable gain equalizer to control the variable gain applied to the input signal.