Adaptive lock position circuit
View Patent ↗An adaptive lock position circuit includes a jitter distribution extremity detector and a phase shifting circuit. The jitter distribution extremity detector receives an input data signal and is operable to compare the input data signal with one or more clock signals derived from a recovered clock signal from a clock and data recovery (CDR) circuit to generate one or more control signals that define the boundaries of a jitter extremity detection window. The phase shifting circuit is coupled in a feedback loop with the jitter distribution extremity detector and receives the one or more control signals from the jitter distribution extremity detector and also receives the recovered clock signal. The phase shifting circuit is operable to shift the phase of the recovered clock signal as a function of the one or more control signals to generate a retiming clock signal such that an edge of the retiming clock signal is interpolated within the jitter extremity detection window.
1. An adaptive lock position circuit, comprising:
a jitter distribution extremity detector that receives an input data signal, the jitter distribution extremity detector being operable to compare the input data signal with a recovered clock signal from a clock and data recovery (CDR) circuit to generate one or more control signals that define boundaries of a jitter extremity detection window; and
a phase shifting circuit coupled in a feedback loop with the jitter distribution extremity detector that receives the one or more control signals from the jitter distribution extremity detector and also receives the recovered clock signal, the phase shifting circuit being operable to shift the phase of the recovered clock signal as a function of the one or more control signals to generate a retiming clock signal such that an edge of the retiming clock signal is interpolated within the jitter extremity detection window.
2. The adaptive lock position circuit of claim 1 , wherein the jitter distribution extremity detector compares the input data signal with one or more clock signals derived from the recovered clock signal to generate the one or more control signals.
3. The adaptive lock position circuit of claim 1 , wherein the retiming clock signal is centered within the jitter extremity detection window.
4. The adaptive lock position circuit of claim 1 , wherein the retiming clock signal is extrapolated using information provided by the jitter distribution extremity detector.
5. The adaptive lock position circuit of claim 1 , wherein the phase shifting circuit receives an interpolated clock setting signal that is used to adjust the phase of the retiming clock signal within the jitter extremity detection window.
6. The adaptive lock position circuit of claim 2 , wherein the jitter distribution extremity detector generates an early control signal that defines a first boundary of the boundaries of the jitter extremity detection window and a late control signal that defines a second boundary of the boundaries of the jitter extremity detection window.
7. The adaptive lock position circuit of claim 6 , wherein the phase shifting circuit generates an early clock signal and a late clock signal by shifting the phase of the recovered clock signal as a function of the early and late control signals, and wherein the early and late clock signals define the jitter extremity detection window.
8. The adaptive lock position circuit of claim 7 , wherein the retiming clock signal is generated from the early and late clock signals.
9. The adaptive lock position circuit of claim 8 , wherein the jitter distribution extremity detector comprises:
a first primary stage latch that samples the retiming clock signal at an edge of the input data signal to generate a phase error signal;
a second primary state latch that samples the early clock signal at an edge of the input data signal to generate a first jitter detection window signal;
a third primary stage latch that samples the late clock signal at an edge of the input data signal to generate a second jitter detection window signal; and
a secondary stage circuitry that generates the early and late control signals by combining the phase error signal and the first and second jitter detection window signals.
10. The adaptive lock position circuit of claim 9 , wherein the secondary stage circuitry comprises:
a first secondary stage latch that samples the phase error signal at an edge of the first jitter detection window signal to generate a first output signal;
a second secondary stage latch that samples the phase error signal at an edge of the second jitter detection window signal to generate a second output signal;
a first logic gate that combines the first output signal and the first jitter detection window signal to generate the early control signal; and
a second logic gate that combines the second output signal and the second jitter detection window signal to generate the late control signal.
11. The adaptive lock position circuit of claim 2 , further comprising:
a charge pump circuit coupled between the jitter distribution extremity detector and the phase shifting circuit, the charge pump circuit being operable to convert the one or more control signals into one or more analog control signals, wherein the phase shifting circuit shifts the phase of the recovered clock signal as a function of the one or more analog control signals.
12. The adaptive lock position circuit of claim 11 , wherein the jitter distribution extremity detector generates an early control signal that defines a first boundary of the boundaries of the jitter extremity detection window and a late control signal that defines a second boundary of the boundaries of the jitter extremity detection window, and wherein the charge pump circuit comprises:
a first DAC counter that converts the early control signal into an analog early control signal; and
a second DAC counter that converts the late control signal into an analog late control signal.
13. The adaptive lock position circuit of claim 12 , wherein the phase shifting circuit comprises:
a first voltage controlled delay circuit that generates an early phase signal as a function of the analog early control signal; and
a second voltage controlled delay circuit that generates a late phase signal as a function of the analog late control signal.
14. The adaptive lock position circuit of claim 13 , wherein:
the charge pump circuit includes a third DAC counter that converts an average of the early control signal and the late control signal into an analog retiming signal; and
the phase shifting circuit includes a third voltage controlled delay circuit that generates the retiming clock signal as a function of the analog retiming signal.
15. The adaptive lock position circuit of claim 14 , wherein the third DAC counter receives an interpolated clock setting signal that adjusts the analog retiming signal in order to adjust the phase of the retiming clock signal within the jitter extremity detection window.
16. The adaptive lock position circuit of claim 11 , wherein:
the jitter distribution extremity detector generates an early control signal that defines a first boundary of the boundaries of the jitter extremity detection window and a late control signal that defines a second boundary of the boundaries of the jitter extremity detection window; and
the charge pump circuit includes a first charge pump operable to convert the early control signal into a first analog signal and a second charge pump operable to convert the late control signal into a second analog signal, wherein the phase shifting circuit shifts the phase of the recovered clock signal as a function of the first and second analog signals.
17. The adaptive lock position circuit of claim 2 , further comprising:
a jitter detection window boundary monitor coupled between the jitter distribution extremity detector and the phase shifting circuit, the jitter detection window boundary monitor being operable to adjust the one or more control signals to maintain a pre-selected ratio of data edges from the input data signal that occur outside of the jitter extremity detection window to data edges from the input data signal that occur within the jitter extremity detection window.
18. The adaptive lock position circuit of claim 17 , wherein:
the jitter distribution extremity detector generates an early control signal that defines a first boundary of the jitter extremity detection window and a late control signal that defines a second boundary of the jitter extremity detection window;
the jitter detection window boundary monitor being operable to adjust the early control signal and the late control signal to maintain the pre-selected ratio.
19. The adaptive lock position circuit of claim 18 , wherein the jitter detection window boundary monitor comprises:
a first pulse generator that generates a first timed signal
a second pulse generator that generates a second timed signal
an early control signal RS latch that receives the early control signal as a set input and receives the first timed signal as a reset input and generates an adjusted early control output; and
a late control signal RS latch that receives the late control signal as a set input and receives the second timed signal as a reset input and generates an adjusted late control output.
20. A method for generating a retiming clock signal for a clock and data recovery circuit, comprising:
receiving an input data signal;
comparing the input data signal with a recovered clock signal from the clock and data recovery circuit to generate one or more control signals that define boundaries of a jitter extremity detection window; and
shifting the phase of the recovered clock signal as a function of the one or more control signals to generate the retiming clock signal such that an edge of the retiming clock signal is interpolated within the jitter detection window.
21. The method of claim 20 , further comprising:
deriving one or more clock signals from the recovered clock signal, wherein the input data signal is compared with the one or more clock signals to generate the one or more control signals that define the boundaries of the jitter extremity detection window.
22. The method of claim 20 , further comprising:
receiving an interpolated clock signal; and
adjusting the phase of the retiming clock signal within the jitter extremity detection window based on the interpolated clock signal.
23. An adaptive lock position circuit, comprising:
means for comparing an input data signal with a recovered clock signal from a clock and data recovery (CDR) circuit to generate one or more control signals that define boundaries of a jitter extremity detection window; and
means for shifting the phase of the recovered clock signal as a function of the one or more control signals to generate a retiming clock signal such that an edge of the retiming clock signal is interpolated within the jitter extremity detection window.
24. The adaptive lock position circuit of claim 23 , wherein the input data signal is compared with one or more clock signals derived from the recovered clock signal to generate the one or more control signals.
25. The adaptive lock position circuit of claim 24 , further comprising:
means for converting the one or more control signals into one or more analog control signals, wherein the phase of the recovered clock signal is shifted as a function of the one or more analog control signals.
26. The adaptive lock position circuit of claim 24 , further comprising:
means for adjusting the one or more controls signals to maintain a pre-selected ratio of data edges from the input data signal that occur outside of the jitter extremity detection window to data edges from the input data signal that occur within the jitter extremity detection window.