System and method for reducing the lock time of a phase locked loop circuit
View Patent ↗In accordance with the teachings described herein, systems and methods are provided for reducing the lock time of a phase locked loop circuit. A phase comparator may be used to detect a phase error between an input reference signal and a feedback clock signal. A frequency synthesizer circuit may be used to control the frequency of an output clock signal as a function of the phase error between the input signal and the feedback clock signal. A feedback divider may be used to divide the frequency of the output clock signal to generate the feedback clock signal. A phase error monitor may be used to detect when the phase error between the input signal and the feedback clock signal reaches a peak value, and in response to detecting the peak value, initialize the feedback divider to reduce the phase error between the input signal and the feedback clock signal.
1. A phase locked loop, comprising:
a phase comparator operable to detect a phase error between an input reference signal and a feedback clock signal;
a frequency synthesizer circuit operable to control the frequency of an output clock signal as a function of the phase error between the input signal and the feedback clock signal;
a feedback divider operable to divide the frequency of the output clock signal to generate the feedback clock signal; and
a phase error monitor operable to detect when the phase error between the input signal and the feedback clock signal reaches a maximum peak phase error value, and in response to detecting the peak phase error value, initialize the feedback divider to reduce the phase error between the input signal and the feedback clock signal.
2. The phase locked loop of claim 1 , wherein the phase comparator generates one or more digital outputs corresponding to the phase error between the input reference signal and the feedback clock signal, and wherein the frequency synthesizer circuit comprises:
a loop filter operable to convert the one or more digital outputs from the phase comparator into a control signal; and
a controlled oscillator operable to generate the output clock signal, the controlled oscillator controlling the frequency of the output clock signal as a function of the control signal.
3. The phase locked loop of claim 1 , wherein:
the feedback divider counts the periods of the output clock signal occurring during each period of the feedback clock signal to generate a counted value signal; and
the phase error monitor receives the counted value signal from the feedback divider and uses the counted value signal to detect the peak value of the phase error between the input signal and the feedback clock signal.
4. The phase locked loop of claim 1 , wherein:
the phase comparator generates one or more output signals corresponding to the phase error between the input reference signal and the feedback clock signal; and
the phase error monitor receives the output signals from the phase comparator and uses the output signals to detect the peak value of the phase error between the input signal and the feedback clock signal.
5. The phase locked loop of claim 1 , wherein the feedback divider is a programmable feedback divider that divides the frequency of the output clock signal by a divide ratio to generate the feedback clock signal.
6. The phase locked loop of claim 5 , further comprising:
a control device operable to program the feedback divider with the divide ratio.
7. The phase locked loop of claim 6 , wherein the control device is further operable to generate a stop signal to the phase error monitor that instructs the phase error monitor to stop initializing the feedback divider.
8. The phase locked loop of claim 7 , wherein the phase error monitor generates the stop signal after the phase error monitor has initialized the feedback divider a pre-selected number of times.
9. The phase locked loop of claim 7 , wherein the phase error monitor generates the stop signal after detecting a lock condition in the phase locked loop.
10. The phase locked loop of claim 7 , wherein the phase error monitor generates the stop signal after a pre-selected period of time has elapsed.
11. The phase locked loop of claim 1 , wherein the phase comparator is a linear phase detector circuit.
12. The phase locked loop of claim 1 , wherein the phase comparator is a non-liner phase detector circuit.
13. A method for reducing the lock time of a phase locked loop circuit, the phase locked loop circuit including a feedback divider for dividing the frequency of an output clock signal to generate a feedback clock signal, the method comprising:
detecting a phase error between an input reference signal and the feedback clock signal;
monitoring the phase error to detect when the phase error reaches a maximum peak value; and
upon detecting that the phase error has reached the peak value, initializing the feedback divider to reduce the phase error between the input reference signal and the feedback clock signal.
14. The method of claim 13 , further comprising:
determining if the feedback clock signal is leading or lagging the input reference signal;
if the feedback clock signal is leading the input reference signal, then monitoring the phase error to detect when the phase error reaches a minimum value, and upon detecting that the phase error has reached the minimum value, initializing the feedback divider; and
if the feedback clock signal is lagging the input reference signal, then monitoring the phase error to detect when the phase error reaches a maximum value, and upon detecting that the phase error has reached the maximum value, initializing the feedback divider.
15. The method of claim 13 , further comprising:
repeating the steps of the method to achieve a feedback loop.
16. The method of claim 15 , further comprising:
detecting a stop signal; and
in response to detecting the stop signal, discontinuing the step of repeating the steps of the method to achieve a feedback loop.
17. A phase locked loop, comprising:
means for detecting a phase error between an input reference signal and a feedback clock signal;
means for controlling the frequency of an output clock signal as a function of the phase error between the input signal and the feedback clock signal;
means for dividing the frequency of the output clock signal to generate the feedback clock signal; and
means for detecting when the phase error between the input signal and the feedback clock signal reaches a maximum peak phase error value, and in response to detecting the peak phase error value, initializing the frequency dividing means to reduce the phase error between the input signal and the feedback clock signal.
18. The phase locked loop of claim 17 , further comprising:
means for programming the frequency dividing means with a divide ratio that is used by the frequency dividing means to generate the feedback clock signal.
19. The phase locked loop of claim 17 , further comprising:
means far generating a stop signal that causes the phase locked loop to stop initializing the frequency dividing means.