Programming of programmable resistive memory devices
View Patent ↗Programming of a programmable resistive memory device includes supplying programming power to the device; generating feedback as to when the device has been programmed; and removing the programming power when the feedback indicates that the device has been programmed.
1. Apparatus for programming selected memory devices in a resistive cross point array of programmable resistive memory devices, the apparatus comprising:
a pre-amplifier for applying a programming potential to a selected one of the memory devices while applying an array potential to other ones of the memory devices, the array and programming potentials being about equal, whereby equipotential isolation of the selected memory device is achieved; and
a circuit for turning off the programming potential when a sense current flowing through the selected memory device indicates that the selected memory device has been programmed.
2. The apparatus of claim 1 , wherein the pre-amplifier has an offset adjust; and wherein prior to programming the circuit adjusts the offset of the pre-amplifier until the array and programming potentials are about equal.
3. The apparatus of claim 2 , wherein adjusting the offset includes supplying a test setup current to the selected memory device, applying the programming potential to the selected memory device, whereby a sense current flows through the selected memory device; and adjusting the offset until the setup current equals the sense current.
4. The apparatus of claim 3 , wherein the circuit provides a test programming current and senses a relationship between the test programming current and the sense current during the programming, the relationship indicating when the selected memory device has been programmed.
5. The apparatus of claim 1 , wherein the pre-amplifier has an offset adjust; and wherein the circuit further provides a test setup current and a test programming current to determine when the offset of the pre-amplifier has been adjusted, the ratio of the test setup current to the test programming current being adjusted as a control parameter to set the sensitivity of the pre-amplifier.
6. The apparatus of claim 4 , wherein the test programming current is supplied to selected memory device while a programming voltage is being applied to the selected memory device; and wherein the programming voltage is removed when a current flowing through the selected memory device is equal to the test programming current.
7. The apparatus of claim 1 , further comprising a FET and a constant current source, an output of the pre-amplifier coupled to a gate of the FET, the constant current source coupled to a first side of a drain-source path of the FET, an input of the pre-amplifier coupled to a second side of the drain-source path.
8. The apparatus of claim 1 , further comprising a programming potential ramp generator for providing the programming potential.