Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same
View Patent ↗The invention is directed to simultaneously etching thin films to different uniform depths depending on positions by using a photoresist pattern having different thickness depending on positions as an etch mask in order to form a contact hole for a gate pad along with at least one other layer, or a data wire and a semiconductor pattern, via a single photolithography step.
1. A thin film transistor (TFT) array panel for a liquid crystal display (LCD), comprising:
a substrate;
a gate line formed on the substrate;
a plurality of common electrodes formed on the substrate;
a gate insulating layer formed on the gate line;
a semiconductor pattern formed on the gate insulating layer;
an ohmic contact layer pattern formed on the semiconductor pattern;
a data wiring pattern comprising a data line, a source electrode and a drain electrode, the source electrode and the drain electrode being formed on the ohmic contact layer pattern;
a plurality of pixel electrodes connected to the drain electrode and arranged parallel to the common electrodes;
a redundant data line arranged parallel to the data line and formed on the data line to overlap the data line; and
a redundant pad being connected to the gate line or the data line,
wherein the common electrodes and the pixel electrodes are formed on the same layer as the gate line.
2. The TFT array panel of claim 1 , further comprising a passivation layer formed on the data wiring pattern.
3. The TFT array panel of claim 2 further comprising a contact hole formed in the passivation layers and exposing the gate line and the data line.
4. The TFT array-panel of claim 3 , wherein the redundant pad is connected to the gate line or the data line through the contact holes of the passivation layer.
5. The TFT array panel of claim 1 , wherein the redundant pad is formed of indium zinc oxide (IZO) or indium tin oxide (ITO).
6. The TFT array panel of claim 1 , wherein the common electrodes and the pixel electrodes are bar shaped.
7. The TFT array panel of claim 1 , wherein the semiconductor pattern has the same shape as the data wiring pattern except for channel portions between the drain electrodes and the source electrodes.
8. The TFT array panel of claim 1 , wherein the redundant pad is connected to the data line,
wherein the redundant data line and the redundant data pad are formed by patterning a conductive layer.
9. The TFT array panel of claim 8 , further comprising a passivation layer covering the data wiring pattern.
10. The TFT array panel of claim 9 , further comprising a contact hole formed in the passivation layer and exposing the data line.
11. The TFT array panel of claim 10 , wherein the redundant data line is connected to the data line through the contact hole.
12. The TFT array panel of claim 1 , wherein the common electrodes and the gate line are formed by patterning a conductive layer.
13. The TFT array panel of claim 1 , wherein the pixel electrodes and the gate line are formed by patterning a conductive layer.
14. The TFT array panel of claim 1 , further comprising a passivation layer formed on the data wiring pattern.
15. The TFT array panel of claim 14 , further comprising a contact hole formed in the passivation layer and exposing the drain electrode, wherein the pixel electrodes are connected to the drain electrodes through the contact hole.
16. The TFT array panel of claim 1 , wherein the data wiring pattern and the semiconductor pattern have a double-step structure.