IP Library Patent Application 10934316
Patent Application
App. No. 10/934,316

Systems and methods for receiving data in a wireless communication network

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Quick Facts
Patent No.
US None
App. No.
10/934,316
Abstract

A method of communicating over a wideband communication channel divided into a plurality of sub-channels comprises dividing a single serial message intended for one of the plurality of communication devices into a plurality of parallel messages, encoding each of the plurality of parallel messages onto at least some of the plurality of sub-channels, and transmitting the encoded plurality of parallel messages to the communication device over the wideband communication channel.

Claims (47)

1 . A transmitter configured for programmable multi-band communication, the transmitter comprising:

a splitting circuit configured to receive a serial data stream and to split the serial data stream into a plurality of parallel data streams;

a phase shifter coupled with the splitting circuit, the phase shifter configured to shift the phase of at least some of the plurality of parallel data streams;

a combiner coupled with the phase shifter, the combiner configured to combine the plurality of parallel data streams into a combined data stream; and

a controller configured to select which of the plurality of data streams will be used for communication by the transmitter.

2 . The transmitter of claim 1 , wherein the splitting circuit comprises a serial to parallel converter.

3 . The transmitter of claim 1 , wherein the phase shifter comprises a plurality of multipliers, each of the plurality of multipliers configured to multiply each of the plurality of data streams with a phase shifting signal.

4 . The transmitter of claim 1 , further comprising a plurality of pulse shappers configured to shape the phase shifted data streams.

5 . The transmitter of claim 1 , wherein the combiner comprises an adder.

6 . The transmitter of claim 1 , wherein the splitting circuit comprises an IFFT.

7 . The transmitter of claim 1 , wherein the combiner comprises a plurality of poly-phased filters.

8 . The transmitter of claim 1 , wherein the splitting circuit, phase shifter, and combiner are programmable, and wherein the controller is configured to program the splitting circuit, phase shifter, and combiner based on how many bands the transmitter is using for communication.

9 . The transmitter of claim 1 , wherein the controller is configured to encode the serial data stream in order to achieve a maximum data rate.

10 . The transmitter of claim 9 , wherein encoding the serial data stream comprises adding zeros into the data stream.

11 . The transmitter of claim 10 , wherein adding zeroes comprises adding two zeroes for every two data bits in the serial data stream, wherein the zeroes are added according to a known rule.

12 . The transmitter of claim 10 , wherein the controller is further configured to select which data bits in the serial data stream will be zero based on which bands the transmitter is using for communication.

13 . The transmitter of claim 10 , further comprising a plurality of delay circuits and a plurality of adders coupled to the splitting circuit, the plurality of delay circuits and the plurality of adders configured to combine each of the plurality of parallel data streams with a delayed version of itself, and combining circuitry coupled with the plurality of adders, the combining circuitry configured to combine the plurality of combined parallel data streams according to predefined plan based on how many bands the transmitter is using for communication.

14 . The transmitter of claim 13 , wherein the combining circuitry comprises adders and subtractors.

15 . The transmitter of claim 13 , wherein the combining circuitry comprises a look-up table.

16 . The transmitter of claim 1 , wherein the combined data stream comprises complex data.

17 . The transmitter of claim 1 , wherein the transmitter further comprises an encoder configured to encode the complex data into values of 1, 0, and −1.

18 . The transmitter of claim 17 , wherein the encoder is configured to encode the complex data into a real and an imaginary data streams.

19 . The transmitter of claim 18 , wherein each of the real and imaginary data streams comprises two data streams, wherein one of the data streams is used to indicate a value of 1, and the other data streams is used to indicate a value of −1.

20 . A transmitter configured for programmable multi-band communication, the transmitter comprising:

a splitting circuit configured to receive a serial data stream and to split the serial data stream into a plurality of parallel data streams;

a phase shifter coupled with the splitting circuit, the phase shifter configured to shift the phase of at least some of the plurality of parallel data streams;

a combiner coupled with the phase shifter, the combiner configured to combine the plurality of parallel data streams into a combined data stream, the combined data stream comprising complex data; and

an encoder configured to encode the complex data of the combined data stream into values of 1, 0, and −1.

21 . The transmitter of claim 20 , wherein the encoder is configured to encode the complex data into a real and an imaginary data streams.

22 . The transmitter of claim 21 , wherein each of the real and imaginary data streams comprises two data streams, wherein one of the data streams is used to indicate a value of 1, and the other data streams is used to indicate a value of −1.

23 . The transmitter of claim 20 , further comprising a controller configured to select which of the plurality of data streams will be used for communication by the transmitter.

24 . The transmitter of claim 23 , wherein the controller is configured to encode the serial data stream in order to achieve a maximum data rate.

25 . The transmitter of claim 23 , wherein encoding the serial data stream comprises adding zeros into the data stream.

26 . The transmitter of claim 25 , wherein adding zeroes comprises adding two zeroes for every two data bits in the serial data stream, wherein the zeroes are added according to a rule known to both the transmitter and receiver.

27 . The transmitter of claim 23 , wherein the controller is further configured to select which data bits in the serial data stream will be zero based on which bands the transmitter is using for communication.

28 . The transmitter of claim 20 , further comprising a plurality of delay circuits and a plurality of adders coupled to the splitting circuit, the plurality of delay circuits and the plurality of adders configured to combine each of the plurality of parallel data streams with a delayed version of itself, and combining circuitry coupled with the plurality of adders, the combining circuitry configured to combine the plurality of combined parallel data streams according to predefined plan based on how many bands the transmitter is using for communication.

29 . The transmitter of claim 28 , wherein the combining circuitry comprises adders and subtractors.

30 . The transmitter of claim 28 , wherein the combining circuitry comprises a look-up table.

31 . The transmitter of claim 20 , wherein the splitting circuit comprises a serial to parallel converter.

32 . The transmitter of claim 20 , wherein the phase shifter comprises a plurality of multipliers, each of the plurality of multipliers configured to multiply each of the plurality of data streams with a phase shifting signal.

33 . The transmitter of claim 20 , further comprising a plurality of pulse shappers configured to shape the phase shifted data streams.

34 . The transmitter of claim 20 , wherein the combiner comprises an adder.

35 . The transmitter of claim 20 , wherein the splitting circuit comprises an IFFT.

36 . The transmitter of claim 20 , wherein the combiner comprises a plurality of poly-phased filters.

37 . The transmitter of claim 20 , wherein the splitting circuit is programmable, and wherein the controller is configured to program the splitting circuit based on how many bands the transmitter is using for communication.

38 . The transmitter of claim 20 , wherein the phase shifter is programmable, and wherein the controller is configured to program the phase shifter based on how many bands the transmitter is using for communication.

39 . The transmitter of claim 20 , wherein the combiner is programmable, and wherein the controller is configured to program the combiner based on how many bands the transmitter is using for communication

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2012
From: PULSE-LINK, INC.
To: INTELLECTUAL VENTURES HOLDING 73 LLC
Reel/Frame 027926/0163 →
SECURITY AGREEMENT Recorded Apr 22, 2009
From: PULSE~LINK, INC.
To: AUDIO MPEG, INC.
Reel/Frame 022575/0704 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2008
From: LAKKIS, ISMAIL
To: PULSE-LINK, INC.
Reel/Frame 020671/0628 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2005
From: LAKKIS, ISMAIL
To: PULSE~LINK, INC.
Reel/Frame 016626/0969 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2005
From: LAKKIS, ISMAIL
To: WIDEBAND ACCESS, INC.
Reel/Frame 016492/0925 →