Integrated circuit having random clock or random delay
An integrated circuit comprising: at least one active device that outputs light during a change in state of the at least one device during operation; a clock circuit configured to output a clock signal to the at least one active device, the clock signal rate being varied so as to hinder optical detection of a pattern of the light during operation of the at least one active device.
1 . An integrated circuit comprising:
at least one active device that outputs light during a change in state of the at least one device during operation;
a clock circuit configured to output a clock signal to the at least one active device, the clock signal rate being varied so as to hinder optical detection of a pattern of the light during operation of the at least one active device.
2 . An integrated circuit according to claim 1 , wherein the clock signal rate is altered randomly or pseudo-randomly.
3 . An integrated circuit according to claim 1 , wherein the rate is varied by introducing a variable delay between a clock source and the at least one active device.
4 . An integrated circuit according to claim 3 , wherein the at least one active device is part of one or more memory circuits of the integrated circuit.