System and method for minimizing noise on a dynamic node
View Patent ↗A circuit for comparing a first match line and a second match line in a CAM circuit. The circuit includes a first keeper circuit having a first input coupled to the second match line and a second keeper circuit having a second input coupled to the first match line. The circuit also includes a third keeper circuit and a fourth keeper circuit. The first and third keeper circuits are coupled to the first match line so as to be capable of maintaining a first voltage level on the first match line. The second and fourth keeper circuits are coupled to the second match line so as to be capable of maintaining a second voltage level on the second match line.
1. A circuit for comparing a first match line and a second match line in a CAM circuit comprising:
a first keeper circuit having a first input coupled to the second match line;
a second keeper circuit having a second input coupled to the first match line;
a third keeper circuit;
a fourth keeper circuit; and
a first NAND gate having a first NAND input coupled to the first match line and a second NAND input coupled to the second match line,
wherein the first keeper circuit includes:
a first PMOS device;
a second PMOS device coupled in series with the first PMOS device, wherein the first input is coupled to a gate of the second PMOS device; and
a second NAND gate having a third NAND input coupled to the first match line and a fourth NAND input coupled to an output of the first NAND gate,
wherein the first and third keeper circuits are coupled to the first match line so as to be capable of maintaining a first voltage level on the first match line, and
wherein the second and fourth keeper circuits are coupled to the second match line so as to be capable of maintaining a second voltage level on the second match line.
2. The circuit of claim 1 , wherein the second keeper circuit includes:
a third PMOS device;
a fourth PMOS device coupled in series with the third PMOS device, wherein the second input is coupled to a gate of the fourth PMOS device; and
a third NAND gate having a fifth NAND input coupled to the second match line and a sixth NAND input coupled to the output of the first NAND gate.
3. The circuit of claim 1 , wherein the third keeper circuit includes a fifth PMOS device having a source coupled to the first match line and a gate coupled to the output of the first NAND gate.
4. The circuit of claim 1 , wherein the fourth keeper circuit includes a sixth PMOS device having a source coupled to the second match line and a gate coupled to the output of the first NAND gate.
5. The circuit of claim 1 , wherein the first local match line is coupled to a first plurality of cam cells and the second local match line is coupled to a second plurality of cam cells.
6. The circuit of claim 1 , wherein the CAM circuit is included in a single die.
7. The circuit of claim 6 , wherein the single die includes a microprocessor.
8. The circuit of claim 1 , wherein the first, second, third and fourth keeper circuits have substantially zero leakage current.
9. A hierarchical CAM circuit comprising:
a first plurality of CAM cells coupled to a first local match line;
a second plurality of CAM cells coupled to a second local match line;
a comparison circuit including:
a first keeper circuit having a first input coupled to the second match line;
a second keeper circuit having a second input coupled to the first match line;
a third keeper circuit;
a fourth keeper circuit; and
a first NAND gate having a first NAND input coupled to the fist match line and a second NAND input coupled to the second match line,
wherein the first keeper circuit includes:
a first PMOS device;
a second PMOS device coupled in series with the first PMOS device, wherein the first input is coupled to a gate of the second PMOS device; and
a second NAND gate having a third NAND input coupled to the first match line and a fourth NAND input coupled to an output of the first NAND gate,
wherein the first and third keeper circuits are coupled to the first match line so as to be capable of maintaining a first voltage level on the first match line, and
wherein the second and fourth keeper circuits are coupled to the second match line so as to be capable of maintaining a second voltage level on the second match line.
10. The circuit of claim 9 , wherein the hierarchical CAM circuit is included in a microprocessor.
11. The circuit of claim 9 , wherein the first, second, third and fourth keeper circuits have substantially zero leakage current.
12. A circuit for comparing a first match line and a second match line in a CAM circuit comprising:
a first keeper circuit having a first input coupled to the second match line;
a second keeper circuit having a second input coupled to the first match line;
a third keeper circuit;
a fourth keeper circuit; and
a first NAND gate having a first NAND input coupled to the first match line and a second NAND input coupled to the second match line,
wherein the first keeper circuit includes:
a first PMOS device;
a second PMOS device coupled in series with the first PMOS device, wherein the first input is coupled to a gate of the second PMOS device; and
a second NAND gate having a third NAND input coupled to the first match line and a fourth NAND input coupled to an output of the first NAND gate,
wherein the first and third keeper circuits are coupled to the first match line so as to be capable of maintaining a first voltage level on the first match line,
wherein the second and fourth keeper circuits are coupled to the second match line so as to be capable of maintaining a second voltage level on the second match line, and
wherein the first, second, third, and fourth keeper circuits have substantially zero leakage current.