Semiconductor integrated circuit device and method for designing the same

1. A semiconductor integrated circuit device comprising:

a plurality of design patterns composed of circuit elements or wires formed on a substrate, respective finished sizes of the plurality of design patterns having a plurality of minimum size values which differ from one design pattern to another depending on a geometric feature of each of the plurality of design patterns,

wherein the plurality of minimum size values are set for a length or width of each of parts composing the circuit elements, a spacing between the parts, an overlapping portion between the parts, and a configuration of a protruding portion of the part, and are set for a width of each of the wires or a spacing between the wires.

2. A semiconductor integrated circuit device comprising:

a plurality of design patterns composed of circuit elements and wires formed on a substrate, respective finished sizes of the plurality of design patterns having a plurality of minimum size values which differ from one design pattern to another depending on a geometric feature of each of the plurality of design patterns,

wherein the circuit elements are contained in an element formation layer and the wires are contained in a wiring layer, the semiconductor integrated circuit device further comprising:

one or more contacts for providing an electric connection between the element formation layer and the wiring layer, the minimum size value of the finished size of each of the contacts depending on an area occupied by the contact on the substrate or on the number of the contacts.

3. A semiconductor integrated circuit device comprising:

a plurality of design patterns composed of circuit elements or wires formed on a substrate, respective finished sizes of the plurality of design patterns having a plurality of minimum size values which differ from one design pattern to another depending on a geometric feature of each of the plurality of design patterns,

wherein the geometric feature is respective directions or positions of the circuit elements or the wires on the substrate, and

the plurality of minimum size values are set to correct dependence of the finished sizes on the directions or positions on the substrate.

4. A semiconductor integrated circuit device comprising:

a plurality of design patterns composed of circuit elements or wires formed on a substrate, respective finished sizes of the plurality of design patterns having a plurality of minimum size values which differ from one design pattern to another depending on a geometric feature of each of the plurality of design patterns,

wherein the circuit elements are bit cells in a memory device,

the geometric feature is a layout type of the bit cells, and

the plurality of minimum size values are set to correct dependence of the finished size on a relationship between a direction in which a gate of a drive transistor extends and a direction in which a gate of an access transistor connected to a word line extends in each of the bit cells.

5. A semiconductor integrated circuit device comprising:

a plurality of design patterns composed of circuit elements or wires formed on a substrate, respective finished sizes of the plurality of design patterns having a plurality of minimum size values which differ from one design pattern to another depending on a geometric feature of each of the plurality of design patterns,

wherein the geometric feature is presence or absence of a dummy pattern which is a dummy of each of the plurality of design patterns contained therein, and

if the dummy pattern is contained in the design pattern, the plurality of minimum size values are set to correct dependence of the finished size on the dummy pattern.

6. A method for designing a semiconductor integrated circuit device, the method comprising a step of:

forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein

a plurality of design rules having different values are applied to the plurality of design patterns by using dependence of respective finished sizes of the plurality of design patterns on a geometric feature of each of the plurality of design patterns, and

the plurality of design rules are applied to a length or width of each of parts composing the circuit elements, a spacing between the parts, an overlapping portion between the parts, and a configuration of a protruding portion of the parts and are applied to a width of each of the wires or a spacing between the wires.

7. A method for designing a semiconductor integrated circuit device, the method comprising the steps of:

forming, on a substrate, a plurality of design patterns composed of circuit elements and wires, and

forming one or more contacts for providing electric connections between the circuit elements and the wires, wherein

a plurality of design rules having different values are applied to the plurality of design patterns by using dependence of respective finished sizes of the plurality of design patterns on a geometric feature of each of the plurality of design patterns, and

any of the plurality of design rules is applied by using dependence of the finished size of each of the contacts on an area occupied by the contact on the substrate or on the number of the contacts.

8. A method for designing a semiconductor integrated circuit device, the method comprising a step of:

forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein

a plurality of design rules having different values are applied to the plurality of design patterns by using dependence of respective finished sizes of the plurality of design patterns on a geometric feature of each of the plurality of design patterns,

the geometric feature is directions or positions of the circuit elements or the wires on the substrate, and

the plurality of design rules are set to correct dependence of the finished sizes on the directions or positions on the substrate.

9. A method for designing a semiconductor integrated circuit device, the method comprising a step of:

forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein

a plurality of design rules having different values are applied to the plurality of design patterns by using dependence of respective finished sizes of the plurality of design patterns on a geometric feature of each of the plurality of design patterns,

the circuit elements are bit cells in a memory device,

the geometric features is a layout type of the bit cells, and

the plurality of design rules are set to correct dependence of the finished size on a relationship between a direction in which a gate of a drive transistor extends and a direction in which a gate of an access transistor connected to a word line extends in each of the bit cells.

10. A method for designing a semiconductor integrated circuit device, the method comprising a step of:

forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein

a plurality of design rules having different values are applied to the plurality of design patterns by using dependence of respective finished sizes of the plurality of design patterns on a geometric feature of each of the plurality of design patterns,

the geometric feature is presence or absence of a dummy pattern which is a dummy of each of the plurality of design patterns contained therein, and

if the dummy pattern is contained in the design pattern, the design rules are set to correct dependence of the finished size on the dummy pattern.