Method for in-place memory interleaving and de-interleaving
View Patent ↗A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address and a number of bits of a different portion of the current address. The current address corresponds to a current location in the memory. In addition, the method includes performing a data swap on data stored at the current location with data stored at the new location.
1. A method of interleaving and de-interleaving a memory, said method comprising:
generating a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address and a number of bits of a different portion of the current address, wherein the current address corresponds to a current location in the memory; and
performing a data swap on data stored at the current location in the memory with data stored at the new location in the memory.
2. The method as recited in claim 1 further comprising updating one or more memory maps by mapping the new address to the current location in the memory and the current address to the new location in the memory.
3. The method as recited in claim 1 , wherein the current address is a cache line address corresponding to one cache line of data.
4. The method as recited in claim 3 , wherein a cache line of data corresponds to 64 bytes of data.
5. The method as recited in claim 3 , wherein the first portion of the current address is the least significant cache line address bits.
6. The method as recited in claim 3 , wherein the different portion of the current address is the most significant cache line address bits.
7. The method as recited in claim 1 , wherein the current address corresponds to an interleaved address.
8. The method as recited in claim 1 , wherein the current address corresponds to a de-interleaved address.
9. The method as recited in claim 1 further comprising iteratively generating a new address for each current address associated with a memory controller until all current addresses have been read.
10. A computer system comprising:
a processor;
a memory controller coupled between the processor and a memory and configured to access a physical location within the memory that is associated with a current address using a map;
wherein, for each address in the map, the memory controller is configured to generate a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address and a same number of bits of a different portion of the current address, wherein the current address corresponds to a current location in the memory; and
wherein, for at least a portion of the new addresses, the memory controller is further configured to cause a data swap to be performed on data stored at the current location in the memory with data stored at the new location in the memory.
11. The computer system as recited in claim 10 , wherein the memory controller is further configured to update the map by mapping the new address to the current location in the memory and the current address to the new location in the memory.
12. The computer system as recited in claim 10 , wherein the current address is a cache line address corresponding to one cache line of data.
13. The computer system as recited in claim 12 , wherein a cache line of data corresponds to 64 bytes of data.
14. The computer system as recited in claim 12 , wherein the first portion of the current address is the least significant cache line address bits.
15. The computer system as recited in claim 12 , wherein the different portion of the current address is the most significant cache line address bits.
16. The computer system as recited in claim 10 , wherein the current address corresponds to an interleaved address.
17. The computer system as recited in claim 10 , wherein the current address corresponds to a de-interleaved address.
18. The computer system as recited in claim 10 further comprising iteratively generating a new address for each current address associated with a memory controller until all current addresses have been read.
19. A computer system comprising:
means for generating a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address and a number of bits of a different portion of the current address, wherein the current address corresponds to a current location in the memory; and
means for performing a data swap on data stored at the current location in the memory with data stored at the new location in the memory.
20. The computer system as recited in claim 19 further comprising means for updating one or more memory maps by mapping the new address to the current location in the memory and the current address to the new location in the memory.
21. A memory system comprising:
a memory;
a memory controller coupled to the memory and configured to access a physical location within the memory that is associated with a current address using a map;
interleave/de-interleave functionality configured to, for each address in the map, generate a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address and a same number of bits of a different portion of the current address, wherein the current address corresponds to a current location in the memory; and
wherein, for at least a portion of the new addresses, the interleave/de-interleave functionality is further configured to cause a data swap to be performed on data stored at the current location in the memory with data stored at the new location in the memory.