Memory

1. A memory comprising:

a memory cell array including a bit line, a word line arranged to intersect with said bit line and memory cells connected between said bit line and said word line,

said memory accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all the memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to a single application of a voltage applied to a nonselected memory cell in the access.

2. The memory according to claim 1 , further performing said recovery so that a memory cell other than a memory cell subjected to said recovery maintains said remanent polarization immediately after said write operation or said remanent polarization subjected to a single application of said voltage applied to said nonselected memory cell in said access.

3. The memory according to claim 1 , wherein

said memory cells include a selected memory cell connected to a selected bit line and a selected word line and a nonselected memory cell other than said selected memory cell,

said memory performing said recovery by applying a first voltage pulse supplying an electric field of a first direction and a second voltage pulse supplying an electric field opposite to said first direction to said memory cells at the same frequency throughout read and rewrite operations performed on said selected memory cell while varying a method of applying said first voltage pulse and said second voltage pulse to said memory cells with first or second data read through said read operation.

4. The memory according to claim 3 , performing said recovery once on each of a plurality of said selected memory cells connected to said selected word line.

5. The memory according to claim 3 , wherein

the voltage of the first voltage pulse and the voltage of the second voltage pulse are substantially ⅓ of a voltage applied to a selected memory cell in said write operation.

6. The memory according to claim 3 , wherein

the voltage of the first voltage pulse and the voltage of the second voltage pulse are substantially half of a voltage applied to said selected memory cell in said write operation.

7. The memory according to claim 3 , applying each of said first voltage pulse and said second voltage pulse once when reading said first data through said read operation, and

applying each of said first voltage pulse and said second voltage pulse twice when reading said second data through said read operation.

8. The memory according to claim 1 , wherein

said memory cells include a selected memory cell connected to a selected word line and a nonselected memory cell other than said selected memory cell,

said memory performing said recovery by applying a first voltage pulse supplying an electric field of a first direction and a second voltage pulse supplying an electric field opposite to said first direction to said memory cells at the same frequency or substantially applying no voltage pulse throughout read and rewrite operations performed on said selected memory cell.

9. The memory according to claim 8 , wherein the memory performs said recovery on a plurality of selected memory cells connected to the selected word line.

10. The memory according to claim 8 , wherein

the voltage of the first voltage pulse and the voltage of the second voltage pulse are substantially ⅓ of a voltage applied to said selected memory cell in said write operation.

11. The memory according to claim 8 , wherein

the voltage of the first voltage pulse and the voltage of the second voltage pulse are substantially half of a voltage applied to said selected memory cell in said write operation.

12. The memory according to claim 1 , wherein

said memory cell array has an hierarchical structure consisting of a plurality of local memory cell arrays including said memory cells.

13. The memory according to claim 12 , wherein

said plurality of local memory cell arrays include a first local memory cell array and a second local memory cell array, and

said memory accesses said first local memory cell array and performs said recovery on said second local memory cell array at the same time.

14. The memory according to claim 1 , further comprising counting means for counting the frequency of access to said memory cells,

in order to perform said recovery in connection with every prescribed access to said memory cells counted by said counting means.

15. The memory according to claim 14 , wherein

said counting means includes a counter for counting the frequency of access to said memory cells.

16. The memory according to claim 1 , further comprising counting means for counting the access time to said memory cells,

in order to perform said recovery in connection with the end of every prescribed access time to said memory cells counted by said counting means.

17. The memory according to claim 16 , wherein

said counting means includes a timer for counting said access time to said memory cells.

18. The memory according to claim 1 , wherein

said voltage applied to a nonselected memory cell in said access is substantially ⅓ of a voltage applied to a selected memory cell in said write operation.

19. The memory according to claim 1 , wherein

said voltage applied to a nonselected memory cell in said access is substantially half of a voltage applied to a selected memory cell in said write operation.

20. The memory according to claim 1 , further comprising a sensing part for determining data of said memory cells on the basis of remanent polarizations of said memory cells in a read operation, wherein

said remanent polarizations subjected to a single application of the voltage applied to said nonselected memory cell in said access allow data determination by said sensing part.

21. The memory according to claim 1 , wherein

said memory cells consist of single ferroelectric capacitors connected between said bit line and said word line.