Method for manufacturing semiconductor device utilizing monitor wafers
View Patent ↗A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.
1. A manufacturing method for a semiconductor device, comprising:
selecting as a monitoring step, one step from a plurality of steps in a main body wafer manufacturing process for manufacturing a main body wafer on which the semiconductor device is formed;
selecting as a variation reduction step, one step from main body postprocess steps succeeding the monitoring step,
the monitoring step being included in a monitor wafer manufacturing process for manufacturing a monitor wafer on which a monitor element is formed,
the monitor wafer manufacturing process including:
a monitor preprocess step;
the monitoring step;
a quality check step of measuring a characteristic of the monitor element formed under the same condition; and
a condition setting step of setting a manufacturing condition in the variation reduction step based on a process influence measured in the quality check step; and
performing the main body postprocess step under the manufacturing condition set in the condition setting step,
the monitoring step comprising an oxidation step for LOCOS formation.
2. A manufacturing method for a semiconductor device according to claim 1 , wherein a gate oxide film formation step is set as the variation reduction step.
3. A manufacturing method for a semiconductor device according to claim 1 , wherein a high-temperature heat treatment step in an interlayer insulating film formation step is set as the variation reduction step.
4. A manufacturing method for a semiconductor device according to claim 1 , wherein a DDD step in a source/drain formation step is set as the variation reduction step.
5. A manufacturing method for a semiconductor device according to claim 1 , wherein the quality check step comprises measuring a CV characteristic of the monitor element.
6. A manufacturing method for a semiconductor device according to claim 1 , wherein the quality check step comprises measuring a length in a process shape of the monitor element.