Conditional precharge design in staticized dynamic flip-flop with clock enable
View Patent ↗A method and apparatus for creating a modified dynamic flip-flop avoids the power waste created by prior art dynamic flip-flops by including a conditional pre-charge control circuit and method. When the modified dynamic flip-flop is in a holding mode, i.e., in the clock disable state, the modified dynamic flip-flop does not use power pre-charging and discharging the internal dynamic node every cycle.
1. A method for providing a modified dynamic flip-flop comprising:
providing a dynamic flip-flop, said dynamic flip-flop having a normal mode of operation and a pre-charge disable mode of operation;
coupling a pre-charge disable circuit to said dynamic flip-flop, wherein;
said pre-charge disable circuit causes said modified dynamic flip-flop to operate in said pre-charge disable mode; and
providing a clock enable signal, wherein;
said pre-charge disable circuit causes said modified dynamic flip-flop to operate in said pre-charge disable mode whenever said clock enable signal is in a first digital state, further wherein;
said pre-charge disable circuit comprises at least a logic GATE; further
wherein:
said logic gate of said pre-charge disable circuit is a NORGATE.
2. A modified dynamic flip-flop comprising:
a dynamic flip-flop;
a pre-charge disable circuit coupled to said dynamic flip-flop, wherein;
said pre-charge disable circuit causes said modified dynamic flip-flop to operate in a pre-charge disable mode such that said dynamic flip-flop has a normal mode of operation and a pre-charge disable mode of operation;
a clock enable signal coupled to said modified dynamic flip-flop, wherein;
said pre-charge disable circuit causes said modified dynamic flip-flop to operate in said pre-charge disable mode whenever said clock enable signal is in a first digital state, further wherein;
said modified dynamic flip-flop operates in said normal mode when said clock enable signal is in a second digital state, further wherein:
said pre-charge disable circuit comprises at least a logic GATE; further
wherein:
said logic gate of said pre-charge disable circuit is a NORGATE.
3. The method for providing a modified dynamic flip-flop of claim 1 wherein:
said first digital state is a digital low state.
4. The method for providing a modified dynamic flip-flop of claim 1 wherein:
said first digital state is a digital low state and said second digital state is a digital high state.
5. The modified dynamic flip-flop of claim 2 wherein:
said first digital state is a digital low state.
6. The modified dynamic flip-flop of claim 2 wherein:
said first digital state is a digital low state and said second digital state is a digital high state.