Adaptive per-pair skew compensation method for extended reach differential transmission
View Patent ↗High speed data transmission schemes often use differential lines to reduce the effect of noise on the data signal. Unfortunately, the signal propagation on the positive and negative lines may be different, which leads to a signal skew problem. This document describes a novel way of compensating for differential line skew in data transmission lines.
1. A differential transmission de-skew system comprising:
a first delay block;
a second delay block;
an output port;
a first subtracter, the first subtracter subtracting an output of the second delay block from an output of the first delay block, where an output of the first subtracter comprises an analog differential signal;
at least one slicer, the at least one slicer converting the analog differential signal to a digital signal, the digital signal exiting through the output port; and
a second subtracter, the second subtracter subtracting the analog differential signal from the digital signal,
wherein the first delay block comprises a plurality of delay cells.
2. The system of claim 1 , wherein delays introduced by the first and second delay blocks are fixed to a system clock.
3. The system of claim 1 , wherein delays introduced by the first and second delay blocks are variable relative to a system clock.
4. The system of claim 1 , wherein a delay introduced by a given delay cell is less than a baud time.
5. The system of claim 1 , wherein the system receives signals from positive and negative leads of a differential transmission cable.
6. The system of claim 5 , wherein the system removes skew between the positive and negative signals.
7. The system of claim 6 , wherein the system adaptively adjusts to remove skew.
8. The system of claim 1 , further comprising a closed feedback control loop, the control loop adjusting at least one delay block in order to minimize skew of signals propagating through the system.
9. The system of claim 1 , wherein the second delay block comprises at least one delay cell.
10. The system of claim 1 , wherein the analog signal comprises a pulse amplitude modulated signal with at least two levels.
11. The system of claim 1 , further comprising an adaptive algorithm block, the adaptive algorithm adjusting delay coefficients of the first and second delay blocks.
12. The system of claim 11 , wherein inputs to the adaptive algorithm include incoming line data, output data, and data error.
13. The system of claim 1 , wherein delay block coefficients are updated every clock cycle.
14. The system of claim 1 , wherein delay block coefficients are updated every at least two clock cycles.
15. A method of de-skewing a differential signal comprising:
propagating a positive signal through a first delay block;
propagating a negative signal through a second delay block;
actively controlling at least one delay block to affect signal propagation, the affected propagation minimizing skew between the positive and negative signals;
subtracting signals exiting the first and second delay blocks with a first subtracter;
slicing an analog signal exiting the first subtracter into a digital output signal; and
subtracting the analog signal exiting the first subtracter from the digital output signal with a second subtracter to create an error signal,
where the first and second delay blocks each comprise a plurality of delay cells.
16. The method of claim 15 , further comprising: using the delayed positive and negative signals, a digital output signal, and an error signal to affect delay block coefficients in at least one delay block.
17. A differential data transmission de-skew system comprising:
a first delay block;
a second delay block;
an output port;
a first subtracter, the first subtracter subtracting an output of the second delay block from an output of the first delay block, where an output of the first subtracter comprises an analog differential signal;
at least one slicer, the at least one slicer converting the analog differential signal to a digital signal, the digital signal exiting through the output port;
a second subtracter, the second subtracter subtracting the analog differential signal from the digital signal; and
a delay control block, the delay control block adjusting delay coefficients of the first and second delay blocks, the delay control block completing a closed feedback control loop, the control loop minimizing skew of signals propagating through the system;
where a delay introduced by a given delay cell is less than a baud time,
where the system receives signals from positive and negative leads of a differential transmission cable,
where the first and second delay blocks each comprise at least one delay cell,
where the analog differential signal comprises a pulse amplitude modulated signal with at least two levels,
where inputs to the delay control block include output data, and error data, and
where delay block coefficients are updated every at least one clock cycles.
18. The system of claim 17 , wherein delays introduced by the first and second delay blocks are fixed to a system clock.
19. The system of claim 17 , wherein delays introduced by the first and second delay blocks are variable relative to a system clock.