System, method and apparatus for an improved MD5 hash algorithm

1. An MD5 arithmetic unit comprising:

a plurality of carry look-ahead adders, wherein the plurality of carry look-ahead adders are configured to execute substantially simultaneously wherein an interim MD5 value Q and a interim MD5 value P are coupled to corresponding inputs of a first one of the plurality of carry look-ahead adders and wherein an interim MD5 value H and a interim MD5 value G are coupled to corresponding inputs of a second one of the plurality of carry look-ahead adders and wherein have an interim MD5 value L and a interim MD5 value K are coupled to corresponding inputs of a third one and a fourth one of the plurality of carry look-ahead adders.

2. The MD5 arithmetic unit of claim 1 , further comprising a 4 to 2 compressor, wherein the corresponding inputs of the first one of the plurality of carry look-ahead adders is coupled to the corresponding pair of outputs of the 4 to 2 compressor.

3. The MD5 arithmetic unit of claim 1 , further comprising a pair of full adders, wherein the pair of full adders are configured to execute substantially simultaneously.

4. The MD5 arithmetic unit of claim 1 , further comprising a control logic having at least one input coupled to at least one of the input of at least one of the plurality of carry look-ahead adders and having at least one input coupled to at least one output of at least one of the plurality of carry look-ahead adders.

5. The MD5 arithmetic unit of claim 4 , further comprising a pair of full adders having two inputs coupled to a corresponding pair of outputs of the 4 to 2 compressor.

6. The MD5 arithmetic unit of claim 5 , wherein the control logic includes:

a first input coupled to an output of the first one of the plurality of carry look-ahead adders;

a second input coupled to a first output of a first one of the pair of full adders;

a third input coupled to a first output of a second one of the pair of full adders; and

a fourth input coupled to an output of a second one of the plurality of carry look-ahead adders.

7. The MD5 arithmetic unit of claim 4 , wherein the pair of full adders are configured to execute substantially simultaneously.

8. The MD5 arithmetic unit of claim 1 , wherein the plurality of carry look-ahead adders include four of carry look-ahead adders.

9. The MD5 arithmetic unit of claim 1 , further comprising a plurality of shift logic.

10. The MD5 arithmetic unit of claim 9 , wherein the plurality of shift logic include:

a shift right logic; and

at least one shift left logic.

11. The MD5 arithmetic unit of claim 9 , wherein the plurality of shift logic are configured to execute substantially simultaneously.

12. The MD5 arithmetic unit of claim 1 , wherein the MD5 arithmetic unit is included on a single die with a microprocessor.

13. The MD5 arithmetic unit of claim 1 , wherein the MD5 arithmetic unit is coupled to a microprocessor.

14. The MD5 arithmetic unit of claim 13 , wherein the MD5 arithmetic unit is coupled to the microprocessor by a bus.

15. The MD5 arithmetic unit of claim 1 , wherein the MD5 arithmetic unit is coupled to a computer.

16. An integrated circuit comprising:

an MD5 arithmetic unit including a plurality of carry look-ahead adders, wherein the plurality of carry look-ahead adders are configured to execute substantially simultaneously wherein an interim MD5 value Q and a interim MD5 value P are coupled to corresponding inputs of a first one of the plurality of carry look-ahead adders and wherein an interim MD5 value H and a interim MD5 value G are coupled to corresponding inputs of a second one of the plurality of carry look-ahead adders and wherein have an interim MD5 value L and a interim MD5 value K are coupled to corresponding inputs of a third one and a fourth one of the plurality of carry look-ahead adders.

17. The integrated circuit of claim 16 , further comprising a microprocessor core coupled to the MD5 arithmetic unit.

18. The integrated circuit of claim 16 , further comprising:

a 4 to 2 compressor;

a pair of full adders having two inputs coupled to a corresponding pair of outputs of the 4 to 2 compressor, wherein the corresponding inputs of the first one of the plurality of carry look-ahead adders is coupled to the corresponding pair of outputs of the 4 to 2 compressor; and

a control logic including:

a first input coupled to an output of the first one of the plurality of carry look-ahead adders;

a second input coupled to a first output of a first one of the pair of full adders;

a third input coupled to a first output of a second one of the pair of full adders; and

a fourth input coupled to an output of a second one of the plurality of carry look-ahead adders.

19. A method of executing an MD5 algorithm comprising:

initializing a plurality of MD5 variables including and X, Y, A, B, C, and D variables;

selecting a MD5 function;

applying the selected MD5 function to the B, C and D variables to produce an interim value E;

applying the X, Y, A and E to a 4 to 2 compressor to produce a pair of outputs including an MD5 interim value Q and an interim value P;

coupling the pair of outputs to a plurality of carry look-ahead adders; and

executing a plurality of carry look-ahead adders substantially simultaneously wherein the interim MD5 value Q and the interim MD5 value P are coupled to corresponding inputs of a first one of the plurality of carry look-ahead adders and wherein an interim MD5 value H and a interim MD5 value G are coupled to corresponding inputs of a second one of the plurality of carry look-ahead adders and wherein have an interim MD5 value L and a interim MD5 value K are coupled to corresponding inputs of a third one and a fourth one of the plurality of carry look-ahead adders.

20. The method of claim 19 , wherein coupling the pair of outputs to the plurality of carry look-ahead adders includes coupling the pair of outputs directly to the first one of the plurality of carry look-ahead adders.

21. The method of claim 19 , wherein coupling the pair of outputs to the plurality of carry look-ahead adders includes:

coupling the pair of outputs to a pair of full adders;

coupling a pair of outputs from the first one of the pair of full adders to a second carry look-ahead adder; and

coupling a pair of outputs from the second one of the pair of full adders to a third carry look-ahead adder and a fourth carry look-ahead adder.

22. The method of claim 21 , further comprising executing the pair of full adders substantially simultaneously.

23. The method of claim 21 , further comprising shifting a corresponding output of each one of the second, third and fourth carry look-ahead adders.

24. The method of claim 23 , further comprising shifting the corresponding output of each one of the second, third and fourth carry look-ahead adders substantially simultaneously.