Apparatus and method for integrated circuit power management
View Patent ↗Methods and/or associated devices and/or systems for providing power management in electronic circuits, including custom ICs, programmable logic devices, and application specific integrated circuits (ASICs) places portions of various power management solutions in the I/O ring or in I/O macros. The invention has numerous specific embodiments and applications to a wide variety of ICs and logic or other circuit design components including circuit modules, software descriptions of circuit modules and/or design or simulation or test systems for circuit development.
1. A method of reducing power usage in an integrated circuit comprising:
establishing separate power islands in said integrated circuit; said power islands separating functional regions in a logic core of said integrated circuit to allow for separated power management of said separate functional regions; said integrated circuit being of a type comprising an I/O ring surrounding said logic core;
establishing one or more power control transistors in said I/O ring of said integrated circuit,
using said one or more power control transistors in said I/O ring to control passage of power to one or more of said power-islands such that said power islands in said logic core; thereby performing a multiplex function in said I/O ring, said multiplex function making available a plurality of different voltage levels for said islands; and are selectively disconnected from a power source by said power control transistors in said I/O ring.
2. The method according to claim 1 further comprising:
providing a control signal generated externally to said one or more power control transistors to said transistors.
3. The method according to claim 2 further wherein:
said control signal is generated by logic located in said integrated circuit.
4. The method according to claim 2 further wherein:
said control signal is generated by logic located external to said integrated circuit.
5. The method according to claim 1 further comprising:
establishing a library of logic descriptions of power transistor I/O cells to allow use of said method with standard integrated circuit computer aided design tools.
6. The method according to claim 1 further comprising:
providing for multiple power inputs to a single power control transistor and/or multiple independently controlled power control transistors to a single power input.
7. The method according to claim 2 further wherein:
said control signal is overdriven.
8. The method according to claim 1 further comprising:
wherein said integrated circuit is a programmable logic device;
wherein said power islands provide power management for two or more different programmable areas of said programmable logic device.
9. The method according to claim 1 further comprising:
integrating electrostatic discharge protection into circuitry enabling said separate power islands.
10. The method according to claim 1 further comprising:
configuring a selector in said I/O ring, said selector making available a plurality of different voltage levels for said islands.
11. The method according to claim 10 further wherein said selector can be placed according to a placement strategy selected from the group consisting of:
corner placement,
expansion of I/O ring size; and
increasing height of I/O cells.
12. The method according to claim 1 further wherein:
using one or more of said power control transistors to provide of said multiplex function said power control transistors located in said I/O ring.
13. The method according to claim 12 further wherein:
at least one of said inputs to said multiplexing function is the output of a power control transistor input of which is the output of a voltage reduction circuit also located in said I/O ring.
14. The method according to claim 10 further wherein:
said multiplexing function is performed in said I/O ring, so that it is transparent to said power island.
15. The method according to claim 1 further wherein:
controls for said transistors are configured such that either one or none will allow passage of power to said power-island, thus providing at least three different power levels to the power-island: VDD 1 , VDD 2 or 0V.
16. The method according to claim 1 further comprising:
placing one or more voltage reduction circuits between said power source and said one or more power control transistors allowing for different virtual power levels to be delivered to said I/C core.
17. The method according to claim 1 further wherein:
said power control transistors can be placed according to a placement strategy selected from the group consisting of:
corner placement;
expansion of I/O ring size; and
increasing height of I/O cells.
18. An information appliance with one or more advanced power control components operated in accordance with the method of claim 1 .
19. An integrated circuit fabrication wafer containing circuitry that when active includes logic operated in accordance with the method of claim 1 .
20. A computer readable medium containing computer interpretable instructions that when loaded into an appropriately configuration information processing device will cause the device to operate in accordance with the method of claim 1 in an emulation system.
21. An integrated circuit device having power management comprising:
a logic core roughly centrally configured on an integrated circuit device, said logic core comprising a large plurality of logic circuits;
one or more power supply inputs, said power supply inputs providing voltage and or current energy for operating said logic core;
an I/O ring roughly surrounding said logic core, said I/O ring providing connections and support circuitry for connecting said logic core to one or more external connections; and
a least one power control transistor in said I/O ring, said power control transistor providing the ability to vary power levels to islands of logic circuits within said logic core, wherein said logic core and said I/O ring including said power control transistors are circuits integrated on a single integrate circuit device, said device connected to other logic through external transmission connections to a plurality of bond pads; thereby performing a multiplex function in said I/O ring, said multiplex function making available a plurality of different voltage levels for said islands.
22. The device according to claim 21 further comprising:
power controller circuitry with-in said logic core, said power control circuitry generating one or more signals controlling said power control transistors.
23. A computer readable medium containing computer interpretable instructions describing a circuit layout for an integrated circuit that, when constructed according to said descriptions, will configure a circuit to embody the apparatus described in claim 21 .