Delay circuit and method with delay relatively independent of process, voltage, and temperature variations
View Patent ↗Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations. In an embodiment, a waveform is received, delayed, and output to an output terminal using at least one relatively low-power device. Supplemental output power is provided by at least one relatively high-power device until the output waveform exceeds a threshold.
1. A method for controlling delay over process, supply-voltage, and temperature variations, comprising:
(a) receiving a waveform;
(b) delaying said waveform;
(c) outputting said delayed waveform to an output terminal using at least one relatively low-power driver transistor;
(d) providing supplemental output drive to said output terminal after an expected period of delay, using at least one relatively high-power driver transistor;
(e) sensing a level of said delayed waveform; and
(f) disabling said at least one high-power driver transistor when the output delayed signal exceeds a threshold.
2. The method of claim 1 , wherein said steps (a) through (e) are performed for rising edge and falling edge portions of the received waveform.
3. The method of claim 1 , further comprising repeating said steps (a) through (e) using the first output delayed signal as a second input signal, thereby further delaying the received waveform while compensating for process, supply-voltage, and temperature variations.
4. An apparatus for controlling delay over process, supply voltage, and temperature variations, comprising:
an input terminal;
an output terminal;
a first path coupled between the input terminal and the output terminal, the first path including at least one relatively low-power output driver transistor that outputs a delayed representation of a received waveform to the output terminal;
a second path coupled between the input terminal and the output terminal, the second path including at least one relatively high-power rising edge output driver transistor that outputs a delayed representation of a rising edge of a received waveform to the output terminal;
a third path coupled between the input terminal and the output terminal, the third path including at least one relatively high-power falling edge output driver transistor that outputs a delayed representation of a falling edge of a received waveform to the output terminal; and
a feedback path including a sensing circuit coupled to an output of the first path, the feedback path including an output coupled to the second path and the third path, wherein the feedback path outputs a feedback signal to the second path and the third path that increasingly disables at least one of the relatively high-power output driver transistors as the waveform output from the first path exceeds a threshold.
5. The apparatus of claim 4 , wherein the at least one relatively low-power output driver transistor includes at least one PMOS transistor and at least one NMOS transistor.
6. The apparatus of claim 5 , wherein the at least one PMOS transistor has a width of approximately 0.93 microns and a length of approximately 0.39 microns, and wherein the at least one NMOS transistor has a width of approximately 0.49 microns and a length of approximately 0.39 microns.
7. The apparatus of claim 4 , wherein the at least one relatively high-power rising edge output driver transistor includes at least one PMOS transistor.
8. The apparatus of claim 7 , wherein the at least one PMOS transistor has a width of approximately 0.93 microns and a length of approximately 0.13 microns.
9. The apparatus of claim 4 , wherein the at least one relatively high-power falling edge output driver transistor includes at least one NMOS transistor.
10. The apparatus of claim 9 , wherein the at least one NMOS transistor has a width of approximately 0.49 microns and a length of approximately 0.13 microns.
11. The apparatus of claim 4 , wherein said sensing circuit senses a voltage level.
12. The apparatus of claim 11 , wherein said sensing circuit comprises an inverter.
13. The apparatus of claim 4 , wherein said sensing circuit senses a current level.
14. The apparatus of claim 13 , wherein said sensing circuit comprises a capacitor.