Structure of semiconductor device with sinker contact region
View Patent ↗A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure. Forming the gate structure includes etching the sinker contact region thereby increasing the first depth of the sinker contact region to a second depth.
1. A semiconductor device, comprising:
a buried layer of a semiconductor substrate;
an active region adjacent at least a portion of the buried layer,
a base layer adjacent at least a portion of the active region;
a dielectric portion adjacent at least a portion of the base layer;
an emitter structure adjacent at least a portion of the base layer;
a sinker contact region of the semiconductor substrate, the sinker contact region formed adjacent at least a portion of the active region when the emitter structure is formed; and
wherein the sinker contact region has a depth of approximately 0.1 to 0.2 microns or approximately 0.3 to 0.6 microns.
2. The semiconductor device of claim 1 , further comprising a collector contact formed at the sinker contact region, the collector contact operable to electrically contact the buried layer.
3. The semiconductor device of claim 1 , further comprising an oxide layer adjacent at least a portion of the buried layer.
4. The semiconductor device of claim 1 , further comprising a first isolation structure adjacent at least a portion of the buried layer.
5. The semiconductor device of claim 4 , further comprising a second isolation structure adjacent at least a portion of the active region.
6. The semiconductor device of claim 4 , wherein the first isolation structure comprises a deep trench.
7. The semiconductor device of claim 4 , further comprising a liner oxide adjacent at least a portion of the first isolation structure.
8. The semiconductor device of claim 5 , wherein the second isolation structure comprises a shallow trench.