IP Library Granted Patent US 7,543,186
Granted Patent B2
US 7,543,186 · App. 10/939,535 · Granted Jun 2, 2009

System and method for implementing software breakpoints

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Quick Facts
Patent No.
US 7,543,186
App. No.
10/939,535
Granted
Jun 2, 2009
Kind
B2
Abstract

The disclosure is directed to a method of loading a breakpoint enabled page of a computer program into a computer readable memory. The method includes identifying a page of a computer program to be loaded into the computer readable memory and reading a breakpoint table to identify a set of breakpoints having memory addresses located within the page of the computer program prior to loading the page of the computer program. Each breakpoint has an instruction address and an instruction storage location. For each of the set of breakpoints, the method includes reading an operating instruction of the page of the computer program located at the instruction address, storing a copy of the operating instruction at the instruction storage location within the breakpoint table, and loading a trap instruction at the instruction address to replace the operating instruction in the page of the computer program to create a breakpoint enabled page of the computer program.

Claims (51)

1. A method of loading a breakpoint enabled page of a computer program into a computer readable memory, the method comprising:

identifying a page of a computer program to be loaded into the computer readable memory;

prior to loading the page of the computer program, reading a breakpoint table to identify a set of breakpoints having memory addresses located within the page of the computer program, each breakpoint in the set of breakpoints having an instruction address, and an instruction storage location, and a task identifier;

for each of the set of breakpoints, reading an operating instruction of the page of the computer program located at the instruction address, storing a copy of the operating instruction at the instruction storage location within the breakpoint table, and loading a trap instruction at the instruction address to replace the operating instruction in the page of the computer program when the task identifier of the respective breakpoint matches a task to be executed as checked before the trap instruction is loaded to replace the operating instruction, to create a breakpoint enabled page of the computer program; and

loading the breakpoint enabled page of the computer program into the computer readable memory, wherein access to the breakpoint table by a debugger routine is prevented during creation and loading of the breakpoint enable page.

2. The method of claim 1 , wherein the computer program has a total size that is greater than the size of the computer readable memory and wherein the page of the computer program has a size that is less than the size of the computer readable memory.

3. The method of claim 1 , further comprising executing at least one of the trap instructions corresponding to at least one of the set of breakpoints and initiating a debug routine in response to executing the trap instruction.

4. The method of claim 3 , further comprising, after executing the at least one trap instruction and after initiating the debug routine, reading the previously stored copy of the operating instruction from the instruction storage location of the breakpoint table and executing the operating instruction to continue execution of the computer program after invocation of the breakpoint.

5. The method of claim 1 , wherein the computer readable memory and a processor configured to execute the instructions in the page of the computer program are disposed within an embedded processor system.

6. The method of claim 5 , wherein the embedded processor system comprises a handheld computer device.

7. The method of claim 6 , wherein the embedded processor system is an MP3 device.

8. The method of claim 5 , wherein the embedded processor system is a personal digital assistant.

9. The method of claim 1 , further comprising loading the breakpoint table from a host computer into the computer readable memory.

10. The method of claim 9 , wherein the host computer includes a debugger routine that is invoked upon execution of at least one of the trap instructions.

11. The method of claim 1 , wherein each task identifier represents a particular program task associated with activation of the breakpoint.

12. The method of claim 11 , wherein when a task other than the particular program task is being executed, the breakpoint is disabled by a real-time operating system kernel program before program execution is halted and when the particular program task is being executed, the breakpoint is enabled by the real-time operating system kernel program.

13. The method of claim 1 , further comprising adjusting a busy flag to prevent a debugger program from accessing the breakpoint table.

14. The method of claim 1 , further comprising evaluating a checksum value associated with the breakpoint table.

15. The method of claim 14 , wherein evaluating the checksum value is performed prior to reading the breakpoint table.

16. A method of loading a breakpoint enabled page of a computer program into a computer readable memory, the method comprising:

identifying a page of a computer program to be loaded into the computer readable memory;

prior to loading the page of the computer program, reading a breakpoint table to identify a set of breakpoints having memory addresses located within the page of the computer program, each breakpoint in the set of breakpoints having an instruction address and an instruction storage location;

for each of the set of breakpoints, reading an operating instruction of the page of the computer program located at the instruction address, storing a copy of the operating instruction at the instruction storage location within the breakpoint table, and loading a trap instruction at the instruction address to replace the operating instruction in the page of the computer program, to create a breakpoint enabled page of the computer program;

loading the breakpoint enabled page of the computer program into the computer readable memory; and

loading the breakpoint table from a host computer into the computer readable memory;

wherein the host computer includes a debugger routine that is invoked upon execution of at least one of the trap instructions, wherein the debugger routine is prevented from accessing the breakpoint table while a memory paging routine within an embedded processor system is in the process of generating and then loading the breakpoint enabled page into the computer readable memory.

17. A method of loading a breakpoint enabled page of a computer program into a computer readable memory, the method comprising:

identifying a page of a computer program to be loaded into the computer readable memory;

prior to loading the page of the computer program, reading a breakpoint table to identify a set of breakpoints having memory addresses located within the page of the computer program, each breakpoint in the set of breakpoints having an instruction address and an instruction storage location;

for each of set of breakpoints, reading an operation instruction of page of the computer program located at the instrucrion address, storing a copy of the operating instruction at the instruction storage location within the breakpoint table, and loading a trap instruction at the instruction at the instruction address to replace the operating instruction in the page of the computer program, to create a breakpoint enabled page of the computer program; and

loading the breakpoint enabled page of the computer program into the computer readable memory, wherein the breakpoint enabled page of the computer memory is to be reading the breakpoint table to identify at least one breakpoint having an address located within the second page of the computer program prior to loading the second page of the computer program into the computer readable memory.

18. The method of claim 17 , further comprising, for the at least one breakpoint, reading an operating instruction of the second page of the computer program located at the instruction address, storing a copy of the operating instruction at the instruction storage location within the breakpoint table for the at least one breakpoint, and loading a trap instruction at the instruction address to replace the operating instruction in the second page of the computer program, to create a breakpoint enabled second page of the computer program.

19. The method of claim 18 , further comprising loading the breakpoint enabled second page of the computer program into the computer readable memory.

20. The method of claim 17 , wherein the second page of the computer program is received from an external media source.

21. The method of claim 20 , wherein the external media source is selected form a hard disk drive, optical storage, and a flash memory.

22. The method of claim 20 , wherein the external media source is within a host computer and wherein the host computer communicates with the computer readable memory using a JTAG interface.

23. An embedded system comprising:

a processor; and

memory accessible to the processor, the memory including:

a breakpoint table including a set of entries, each entry of the set of entries identifying an instruction address and including a storage cell for a replaced instruction and including a task identifier; and

computer implemented instructions operable by the processor to access the breakpoint table and when the task identifier matches a task to be executed to insert a trap instruction associated with each of the set of entries included in the breakpoint table at the identified instruction addresses within a program page prior to loading the program page with the trap instruction for execution, wherein access to the breakpoint table by a debugger routine is prevented during creation and loading of the breakpoint enabled page.

24. The embedded system of claim 23 , wherein the memory has an available capacity that is smaller than a program associated with the program page.

25. A system comprising:

a host computer including debugger software; and

an embedded system accessible to the host computer, the embedded system including:

a processor; and

memory accessible to the processor, the memory including:

a breakpoint table including a set of entries, each entry of the set of entries identifying an instruction address associated with an instruction included in a page of a program that is to be replaced by a trap instruction, each entry including a storage cell for storing the replaced instruction, each entry including a task identifier for identifying a task to be executed, wherein the memory includes computer instructions operable by the processor to access the breakpoint table and when the task identifier matches a task to be executed to insert the trap instruction at the instruction address within the page prior to loading the page with the trap instruction for execution, wherein access to the breakpoint table by a debugger routine is prevented during creation and loading of the breakpoint enabled page.

26. The system of claim 25 , wherein the breakpoint table is created by the debugger software and transferred to the embedded system.

27. The system of claim 25 , wherein a capacity of the memory is less than a size of the program.

28. The system of claim 25 , wherein the program is stored on a media source accessible to the memory.

Assignments (27)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 037354 FRAME: 0773. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT RELEASE. Recorded Aug 15, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, LLC
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0823 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2015
From: SIGMATEL LLC
To: INTEL CORPORATION
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RELEASE OF SECURITY INTEREST Recorded Jan 23, 2015
From: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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RELEASE OF SECURITY INTEREST Recorded Jan 23, 2015
From: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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RELEASE OF SECURITY INTEREST Recorded Jan 23, 2015
From: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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RELEASE OF SECURITY INTEREST Recorded Jan 23, 2015
From: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034799/0777 →
SECURITY AGREEMENT Recorded Nov 12, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 17, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030628/0636 →
SECURITY AGREEMENT Recorded May 10, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024358/0439 →
SECURITY AGREEMENT Recorded Mar 16, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A.
Reel/Frame 024079/0406 →
SECURITY AGREEMENT Recorded Sep 23, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 023273/0099 →
SECURITY AGREEMENT Recorded Jul 9, 2008
From: SIGMATEL, INC.
To: CITIBANK, N.A.
Reel/Frame 021212/0372 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2004
From: SCHULTZ, RUSSELL A.
To: SIGMATEL, INC.
Reel/Frame 015801/0562 →