SIMD processor having enhanced operand storage interconnects
View Patent ↗A SIMD processor includes an ALU having data interconnects facilitating the concurrent processing of overlapping data portions of at least one operand store. Such interconnects facilitate the calculation of shift-invariant convolutions, and sum of absolute differences between an operand in the operand store and another operand.
1. A single instruction multiple data (SIMD) processor comprising:
an arithmetic logic unit (ALU) comprising:
a plurality of logic blocks, each of said logic blocks comprising a first set of inputs and a second set of inputs;
a plurality of first interconnects comprising Nxm i data lines, interconnecting a plurality of N data portions of a first operand to said first inputs of each of said logic blocks, thereby providing the same data to said first set of inputs of each of said logic blocks, wherein said first operand represents data in the form a(0)a(1)a(2). . . a(P−1) , wherein each a(i) represents one of said data portions of said first operand, and wherein said plurality of first interconnects provides N data portions of said data in the form, a(j)a(j+1). . . a(j+N−1), to said first set of inputs of each of said logic blocks, where P>N;
a plurality of groups of second interconnects, each of said groups comprising Nxm 2 data lines and interconnecting a different subset of N data portions of a second operand to each of said second set of inputs of said plurality of logic blocks, with each of said subsets of N data portions of said second operand having data units in at least one other of said subsets of N data portions of said second operand, wherein said second operand represents data in the form x(0)x(1)x(2). . . wherein each x(i) represents one of said data portions of said second operand, and wherein each of said second group of interconnects provides a subset of said data portions in said second operand in the form x(n)x(n+1). . . x(n+N−1), to second inputs of an interconnected one of said logic blocks;
wherein each of said logic blocks calculates, from data at its first and second inputs,
a(j)*x(n)+a(j+1)*x(n+1) . . . +a(j+N−1)*x(n+N−1).
2. The processor of claim 1 , wherein N=4.
3. The processor of claim 1 , wherein each of said logic blocks is further operable to calculate, from data at its first and second inputs,
|a(j)−x(i)|+|a(j+1)−x(i+1)|+ . . . +|a(j+N−1)−x(i+N−1)|
in dependent on an instruction provided to said processor.
4. The processor of claim 1 , wherein said processor comprises 1st to kth logic blocks, and for the of said logic block n=i−1.
5. The processor of claim 1 , wherein said processor comprises 1 st to kth logic blocks, and for the ith of said logic block n=i.
6. The processor of claim 5 , wherein j=0.
7. The processor of claim 5 , further comprising a combining circuit to form a combined output of said logic blocks, to provide a result of the form
y(0)y(1) . . . y(k)
where each y(i)=a(j)*x(i)+a(j+1)*x(i+1) . . . +a(j+N−1) *x(i+N−1) and is provided by one of said logic blocks.
8. The processor of claim 7 , further comprising a resultant register for storing said result.
9. The processor of claim 5 , wherein each a(i) comprises m bits.
10. The processor of claim 9 , wherein each x(i) comprises m bits.
11. The processor of claim 10 , further comprising a first register, and wherein said first operand is obtained by reading data from said first register.
12. The processor of claim 11 , further comprising a second register, and wherein said second operand is obtained by reading data from said second register.
13. The processor of claim 10 , wherein said first operand is obtained by reading data from a memory location within processor readable memory interconnected with said processor.
14. The processor of claim 13 , wherein said second operand is obtained by reading data from a memory location within processor readable memory interconnected with said processor.