Memory device with floating gate stack

1. A memory device comprising:

a substrate including isolation regions and active regions;

a floating gate stack proximate the substrate, the floating gate stack comprising:

a first high-k dielectric layer proximate the substrate;

a first metal layer proximate the first high-k dielectric layer;

a second high-k dielectric layer proximate the first metal layer;

a second metal layer proximate the second high-k dielectric layer; and

a third high-k dielectric layer proximate the second metal layer; and

a control gate electrode proximate the floating gate stack.

2. The memory device of claim 1 , wherein the floating gate stack further comprises:

a third metal layer proximate the third high-k dielectric layer; and

a fourth high-k dielectric layer proximate the third metal layer.

3. The memory device of claim 1 , wherein the second high-k dielectric layer comprises at least one of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, and PMN.

4. The memory device of claim 3 , wherein the second high-k dielectric layer is incorporated with N.

5. The memory device of claim 3 , wherein the second high-k dielectric layer comprises a mixture comprising at least one of TiN, HfN, TaN, ZrN, and LaN.

6. The memory device of claim 1 , wherein the first high-k dielectric layer has a thickness within a range of 1 Å to 50 Å.

7. The memory device of claim 1 , wherein the first metal layer comprises one of TiN, HfN, TaN, ZrN, and LaN.

8. The memory device of claim 1 , wherein the first metal layer has a thickness within a range of 1 Å to 50 Å.

9. The memory device of claim 1 , wherein the first high-k dielectric layer and the second high-k dielectric layer comprise similar materials.

10. The memory device of claim 1 , wherein the first high-k dielectric layer and the second high-k dielectric layer comprise different materials.

11. The memory device of claim 1 , wherein the floating gate stack has a thickness within a range of 20 Å to 500 Å.

12. The memory device of claim 1 , wherein the first metal layer is partially oxidized and the first high-k dielectric layer and the second high-k dielectric layer are incorporated with N from the oxidation.

13. An electrically-erasable programmable read-only memory comprising:

a plurality of memory cells formed on a substrate, each memory cell comprising:

isolation regions and active regions in the substrate;

a floating gate stack proximate the substrate, the floating gate stack comprising:

a first high-k material layer proximate the substrate;

a first metal floating gate electrode proximate the first high-k material layer;

a second high-k material layer proximate the first metal floating gate electrode;

a second metal floating gate electrode proximate the second high-k material layer; and

a third high-k material layer proximate the second metal floating gate electrode; and

a control gate electrode proximate the floating gate stack.

14. The memory of claim 13 , wherein the first high-k material layer and the second high-k material layer comprise similar high-k materials.

15. The memory of claim 13 , wherein the first high-k material layer and the second high-k material layer comprise different high-k materials.

16. The memory of claim 13 , wherein the first high-k material layer comprises one of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, and PMN.

17. The memory of claim 16 , wherein the first high-k material layer comprises a mixture of at least two of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, and PMN.

18. The memory of claim 16 , wherein the first high-k material layer comprises a mixture comprising at least one of TiN, HfN, TaN, ZrN, and LaN.

19. The memory of claim 16 , wherein the second high-k material layer comprises one of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO O 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, and PMN.

20. The memory of claim 19 , wherein the third high-k material layer comprises one of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, and PMN.

21. The memory of claim 13 , wherein the first metal floating gate electrode comprises one of TiN, HfN, TaN, ZrN, and LaN.

22. The memory of claim 21 , wherein the second metal floating gate electrode comprises one of TiN, HfN, TaN, ZrN, and LaN.

23. A method of making a memory device, the method comprising:

forming isolation regions, well regions, and active regions on a substrate;

depositing a first high-k material layer on the substrate;

depositing a first metal layer on the first high-k material layer;

depositing a second high-k layer material layer on the first metal layer;

depositing a second metal layer on the second high-k material layer; and

depositing a third high-k material layer on the second metal layer.

24. The method of claim 23 , wherein depositing the second high-k dielectric layer comprises simultaneously depositing at least two of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , Zro 2 , ZrSiO, La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, PMN, TiN, HfN, TaN, ZrN, and LaN.

25. The method of claim 23 , further comprising:

annealing the substrate, the first high-k material layer, the first metal layer, the second high-k material layer, the second metal layer, and the third high-k material layer to partially oxidize the first metal layer and the second metal layer.

26. The method of claim 25 , further comprising:

depositing a gate electrode material layer on the third high-k material layer.

27. The method of claim 23 , further comprising:

depositing a third metal layer on the third high-k material layer; and

depositing a fourth high-k material layer on the third metal layer.

28. The method of claim 23 , wherein the first high-k material layer is deposited using atomic layer deposition.

29. The method of claim 23 , wherein the first high-k material layer is deposited using one of metal-organic chemical vapor deposition, plasma vapor deposition, and jet vapor deposition.

30. The method of claim 23 , wherein the first metal layer is deposited using atomic layer deposition.

31. The method of claim 23 , wherein the first metal layer is deposited using one of metal-organic chemical vapor deposition, plasma vapor deposition, and jet vapor deposition.

32. The method of claim 27 , further comprising:

depositing a gate electrode material layer on the fourth high-k material layer.

33. The method of claim 23 , wherein depositing the first high-k dielectric material layer comprises depositing at least one of Si 3 N 4 , Al 2 O 3 , Ta 2 O 5 , HfO 2 , TiO 2 , HfSiO x , ZrO 2 , ZrSiO x , La 2 O 3 , CeO 2 , Bi 4 Si 2 O 12 , WO 3 , Y 2 O 3 , LaAlO 3 , BST, PST, PZN, PZT, and PMN.

34. The method of claim 23 , wherein depositing the first metal layer comprises depositing at least one of TiN, HfN, TaN, ZrN, and LaN.

35. The method of claim 34 , further comprising:

annealing the substrate, the first high-k material layer, the first metal layer, the second high-k material layer, the second metal layer, and the third high-k material layer to partially oxidize the first metal layer and the second metal layer to incorporate N into the first high-k material layer, the second high-k material layer, and the third high-k material layer.

36. A flash memory device comprising:

a plurality of memory cells formed on a substrate, each memory cell comprising:

isolation regions and active regions in the substrate;

a floating gate stack proximate the substrate, the floating gate stack comprising:

a first high-k material layer proximate the substrate;

a first metal floating gate electrode proximate the first high-k material layer;

a second high-k material layer proximate the first metal floating gate electrode;

a second metal floating gate electrode proximate the second high-k material layer; and

a third high-k material layer proximate the second metal floating gate electrode; and

a control gate electrode proximate the floating gate stack.