IP Library Granted Patent US 7,256,457
Granted Patent B2
US 7,256,457 · App. 10/941,543 · Granted Aug 14, 2007

Thin-film transistor device, utilizing different types of thin film transistors

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Quick Facts
Patent No.
US 7,256,457
App. No.
10/941,543
Granted
Aug 14, 2007
Kind
B2
Abstract

A TFT device, a method of manufacturing the same, a TFT substrate and a display device, making it possible to decrease the photolithography steps, to improve the productivity and to decrease the cost of production. There are formed on the same substrate a first n-ch TFT having an LDD region which is entirely covered with a gate electrode, a second n-ch TFT having an LDD region partially covered with a gate electrode, and a p-ch TFT. Here, electrically conducting thin films and a gate electrode are formed on the electrically conducting thin film and on the insulating film, phosphorus ions are implanted into source/drain regions of the n-ch TFTs using the electrically conducting thin films and gate electrode as masks, and a gate electrode is formed by etching the electrically conducting thin film by using the electrically conducting thin film as a mask.

Claims (23)

1. A thin-film transistor device comprising:

a first thin-film transistor of n-type of electric conduction having a first channel region, a first low-concentration impurity region and a first gate electrode covering nearly the whole first low-concentration impurity region and the first channel region;

a second thin-film transistor of n-type of electric conduction having a second channel region, a second low-concentration impurity region and a second gate electrode covering part of the second low-concentration impurity region and the second channel region; and

a third thin-film transistor of p-type of electric conduction having a third channel region and a third gate electrode covering the third channel region,

wherein:

the impurities are contained at different concentrations in the first and second channel regions and in the third channel region; and

the first and second gate electrodes have a different layer structure or are formed from different materials than the third gate electrode.

2. A thin-film transistor device according to claim 1 , wherein the first and second channel regions contain impurities of the p-type only, and the third channel region contains both p-type impurities and n-type impurities.

3. A thin-film transistor substrate having a plurality of bus lines formed on a base substrate in a manner intersecting one another via an insulating film, and thin-film transistor devices formed in pixel regions arranged like a matrix on a display region on the base substrate and in peripheral circuits arranged surrounding the display region, wherein the thin-film transistor devices include thin-film transistor devices according to claim 1 .

4. A display device having a substrate provided with thin-film transistors as switching elements, wherein the substrate is a thin-film transistor substrate according to claim 3 .

5. A thin-film transistor device according to claim 1 , wherein the first to third channel regions contain impurities of the p-type only, and the first and second channel regions contain impurities of the p-type at a concentration higher than that in the third channel region.

6. A thin-film transistor device according to claim 5 , wherein the first and second gate electrodes are formed by using a first electrically conducting material, and the third gate electrode is formed by using a second electrically conducting material different from the first electrically conducting material.

7. A thin-film transistor device according to claim 5 , wherein the first and second gate electrodes are formed by using a first electrically conducting material, and the third gate electrode has a laminated layer structure including a first layer formed by using a second electrically conducting material different from the first electrically conducting material and a second layer formed by using the first electrically conducting material on the first layer.

8. A thin-film transistor device according to claim 5 , wherein the first and second gate electrodes have a laminated layer structure including a first layer formed by using a first electrically conducting material and a second layer formed on the first layer by using a second electrically conducting material different from the first electrically conducting material and having a width larger than that of the first layer, and the third gate electrode is formed by using the first electrically conducting material.

9. A thin-film transistor device comprising:

a first thin-film transistor of n-type of electric conduction having a first channel region, a first low-concentration impurity region and a first gate electrode covering nearly the whole first low-concentration impurity region and the first channel region;

a second thin-film transistor of n-type of electric conduction having a second channel region, a second low-concentration impurity region and a second gate electrode covering part of the second low-concentration impurity region and the second channel region; and

a third thin-film transistor of p-type of electric conduction having a third channel region and a third gate electrode covering the third channel region,

wherein:

the impurities are contained at different concentrations in the first and second channel regions and in the third channel region;

the first and second gate electrodes and the third gate electrode are formed in different structures or by using different materials;

the first to third channel regions contain impurities of the p-type only, and the first and second channel regions contain impurities of the p-type at a concentration higher than that in the third channel region; and

the first and second gate electrodes have a laminated layer structure including a first layer formed by using a first electrically conducting material and a second layer formed on the first layer by using a second electrically conducting material different from the first electrically conducting material and having a width larger than that of the first layer, and the third gate electrode has a laminated layer structure including a third layer formed by using the first electrically conducting material and a fourth layer formed on the third layer by using the second electrically conducting material and having a width nearly the same as that of the third layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2005
From: FUJITSU LIMITED
To: SHARP KABUSHIKI KAISHA
Reel/Frame 016345/0210 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2005
From: FUJITSU DISPLAY TECHNOLOGIES CORPORATION
To: FUJITSU LIMITED
Reel/Frame 016345/0310 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2004
From: HOTTA, KAZUSHIGE
To: FUJITSU DISPLAY TECHNOLOGIES CORPORATION
Reel/Frame 015806/0960 →