IP Library Granted Patent US 7,075,316
Granted Patent B2
US 7,075,316 · App. 10/941,605 · Granted Jul 11, 2006

Capacitance detector circuit, capacitance detection method, and fingerprint sensor using the same

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Quick Facts
Patent No.
US 7,075,316
App. No.
10/941,605
Granted
Jul 11, 2006
Kind
B2
Abstract

A capacitance detecting circuit of a capacitive sensor having a plurality of column lines and a row line intersecting the column lines detects a change in capacitance at an intersection of a column line and a row line. The circuit includes a PN code generating unit for generating a code having orthogonality in time sequence to output the generated code as a column drive signal, a column line drive unit for driving a predetermined one of the column lines which are selected in response to the code, a capacitance detecting unit, connected to the row line, for detecting a voltage by converting a total sum of changes in capacitance at intersections of the selected column lines into the voltage to output the detected voltage, and a decode processing unit for performing a predetermined calculation on the detected voltage output from the capacitance detecting unit and the code to determine a voltage value responsive to the capacitance change at the intersection.

Claims (53)

1. A circuit of a capacitive sensor having a plurality of column lines and a row line intersecting the column lines, for detecting a change in capacitance at an intersection of a column line and a row line, the circuit comprising:

code generating means for generating a code having orthogonality in time sequence to output the generated code as a column drive signal;

column line drive means for driving a plurality of column lines, from among the column lines that are selected in response to the code;

capacitance detecting means, connected to the row line, for detecting a voltage by converting a total sum of changes in capacitance at intersections of the selected column lines into the voltage to output the detected voltage; and

decode processing means for performing a predetermined calculation on the detected voltage output from the capacitance detecting means and the code to determine a voltage value responsive to the capacitance change at the intersection,

wherein the code generating means generates a PN code, and outputs the PN code with the phase thereof varied in time sequence, and

wherein the code generating means repeats by a plurality of times a circle within which the phase of the PN code is varied by a number of bits equal to the number of bits of the PN code, and wherein the decode processing means determines a voltage responsive to a chanee in capacitance at the intersection on a per cycle basis, sums the voltage for a plurality of cycles, and outputs the summed result as the detected voltage.

2. A circuit according to claim 1 , wherein the code generating means generates a plurality of PN codes, and switches the PN code from one PN code to a different PN code every cycle.

3. A circuit according to claim 1 , wherein the PN code comprises an M sequence.

4. A circuit according to claim 1 , wherein a capacitance at an intersection is detected in an area type capacitive sensor which includes a matrix of intersections of a plurality of column lines and a plurality of row lines.

5. A circuit according to claim 1 , wherein a capacitance at an intersection is detected in a line type capacitive sensor which includes a single row line and a plurality of column lines intersecting the row line.

6. A fingerprint sensor comprising a circuit according to claim 1 .

7. A circuit of a capacitive sensor having a plurality of column lines and a row line intersecting the column lines, for detecting a change in capacitance at an intersection of a column line and a row line, the circuit comprising:

code generating means for generating a code having orthogonality in time sequence to output the generated code as a column drive signal;

column line drive means for driving a plurality of column lines, from among the column lines that are selected in response to the code;

capacitance detecting means, connected to the row line, for detecting a voltage by converting a total sum of changes in capacitance at intersections of the selected column lines into the voltage to output the detected voltage; and

decode processing means for performing a predetermined calculation on the detected voltage output from the capacitance detecting means and the code to determine a voltage value responsive to the capacitance change at the intersection,

wherein the code generating means generates a Walsh code having bit strings varying in time sequence, and outputs the Walsh code as the code thereof.

8. A circuit according to claim 7 , wherein a capacitance at an intersection is detected in an area type capacitive sensor wbich includes a matrix of intersections of a plurality of column lines and a plurality of row lines.

9. A circuit according to claim 7 , wherein a capacitance at an intersection is detected in a line type capacitive sensor which includes a single row line and a plurality of column lines intersecting the row line.

10. A fingerprint sensor comprising a circuit according to claim 7 .

11. A circuit of a capacitive sensor having a plurality of column lines and a row line intersecting the column lines, for detecting a change in capacitance at an intersection of a column line and a row line, the circuit comprising:

code generating means for generating a code having orthogonality in time sequence to output the generated code as a column drive signal;

column line drive means for driving a plurality of column lines, from among the column lines that are selected in response to the code;

capacitance detecting means connected to the row line, for detecting a voltage by converting a total sum of changes in capacitance at intersections of the selected column lines into the voltage to output the detected voltage; and

decode processing means for performing a predetermined calculation on the detected voltage output from the capacitance detecting means and the code to determine a voltage value responsive to the capacitance change at the intersection,

wherein the decode processing means performs a decode process by multiplying and summing a data string of the detected voltage that is output in accordance wit the code in time sequence.

12. A circuit according to claim 11 , wherein a capacitance at an intersection is detected in an area type capacitive sensor which includes a matrix of intersections of a plurality of column lines and a plurality of row lines.

13. A circuit according to claim 11 , wherein a capacitance at an intersection is detected in a line type capacitive sensor which includes a single row line and a plurality of column lines intersecting the row line.

14. A fingerprint sensor comprising a circuit according to claim 11 .

15. A circuit for detecting a change in capacitance at an intersection of a column line and a row line in a capacitive sensor that includes a plurality of column lines and a row line intersecting the column lines, the circuit comprising:

code generating means for generating a code having orthogonality in time sequence;

column line group selecting means for dividing the plurality of column lines into groups, each group including a predetermine number of column lines, and for selecting a group of column lines to be measured;

column line drive means for driving the plurality of column lines in each of the successively selected column line groups in response to the code;

capacitance detecting means, connected to the row line, for converting a total sum of changes in capacitance at intersections of the selected column lines into a voltage signal, and outputting the voltage signal as a detected voltage; and

decode processing means for performing a predetermined calculation on the measured voltage and the code on a per column line group basis, and for determining a voltage value responsive to the capacitance change at each intersection,

wherein the code generating means generates a PN code, and outputs the PN code with the phase thereof varied in time sequence, and

wherein the code generating means repeats by a plurality of times a cycle within which the phase of the PN code is varied by a number of bits equal to the number of bits of the PN code, and wherein the decode processing means determines a voltage responsive to a change in capacitance at the intersection on a per cycle basis, sums the voltage for plurality of cycles, and outputs the summed result as the detected voltage.

16. A circuit according to claim 15 , wherein the column line group comprises a predetermined number of adjacent column lines.

17. A circuit according to claim 15 , wherein the column line group comprises column lines spaced at predetermined intervals.

18. A circuit according to claim 15 , wherein the code generating means generates a plurality of PN codes, and switches the PN code from one PN code to a different PN code every cycle.

19. A circuit according to claim 15 , wherein the PN code comprises an M sequence.

20. A fingerprint sensor comprising a capacitance detection circuit according to claim 15 .

21. A circuit for detecting a change in capacitance at an intersection of a column line and a row line in a capacitive sensor that includes a plurality of column lines and a row line intersecting the column lines, the circuit comprising:

code generating means for generating a code having orthogonality in time sequence;

column line group selecting means for dividing the plurality of column lines into groups, each group including a predetermine number of column lines, and for selecting a group of column lines to be measured;

column line drive means for driving the plurality of column lines in each of the successively selected column line groups in response to the code;

capacitance detecting means, connected to the row line, for converting a total sum of changes in capacitance at intersections of the selected column lines into a voltage signal, and outputting the voltage signal as a detected voltage; and

decode processing means for performing a predetermined calculation on the measured voltage and the code on a per column line group basis, and for determining a voltage value responsive to the capacitance change at each intersection,

wherein the code generating means generates a Walsh code having bit strings varying in time sequence, and outputs the Walsh code as the code thereof.

22. A fingerprint sensor comprising a capacitance detection circuit according to claim 21 .

23. A circuit according to claim 21 , wherein the column line group comprises a predetermined number of adjacent column lines.

24. A circuit according to claim 21 , wherein the column line group comprises column lines spaced at predetermined intervals.

Assignments (3)
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2016
From: ALPS ELECTRIC CO. LTD.
To: SYNAPTICS INCORPORATED
Reel/Frame 038638/0447 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2004
From: UMEDA, YUICHI; SATO, JUNICHI
To: ALPS ELECTRIC CO., LTD.
Reel/Frame 015794/0941 →