Granted Patent B2

US 7,483,595 · App. 10/941,859 · Granted Jan 27, 2009

Abstract

Claims (40)

1. A method, comprising:

processing multiple rows of pixels of an image simultaneously with a single instruction, wherein the processing includes building the multiple rows of pixels of the image in a plurality of horizontal load registers and a plurality of vertical load registers that are arranged with respect to each other to correspond with the image;

shifting pixels from a first vertical load register of the plurality of vertical load registers into a second vertical load register of the plurality of vertical load registers; and

shifting at least one pixel from each of the plurality of horizontal load registers into the first vertical load register.

2. The method according to claim 1 , wherein the processing includes processing of multiple rows of pixels that are stored in non-sequential locations in a memory.

3. The method according to claim 1 , wherein each of the pixels represents one bit.

4. The method according to claim 1 , wherein shifting pixels into the second vertical load register and into the first vertical load register further comprises:

simultaneously shifting the pixels from the first vertical load register into the second vertical load register and shifting the at least one pixel from each of the plurality of horizontal load registers into the first vertical load register.

5. The method according to claim 1 , wherein shifting the at least one pixel from each of the plurality of horizontal load registers into the first vertical load register further comprises:

shifting one pixel corresponding to a most significant bit from each of the plurality of horizontal load registers into the first vertical load register.

6. The method according to claim 1 , wherein a number of the horizontal and vertical load registers provided is based on an imaging algorithm used.

7. A method, comprising:

selecting pixel windows having a plurality of pixels of an image spanning across multiple rows and columns;

building a plurality of vertical and horizontal load registers to include the plurality of pixels of the selected pixel windows; and

simultaneously processing selected pixels of the plurality of pixels included in the plurality of vertical and horizontal load registers using a single instruction;

shifting pixels from a first vertical load register of the plurality of vertical load registers into a second vertical load register of the plurality of vertical load registers; and

shifting at least one pixel from each of the plurality of horizontal load registers into the first vertical load register.

8. The method according to claim 7 , wherein the shifting of at least one pixel from each of the plurality of horizontal load registers into the first vertical load register further comprises:

shifting one pixel corresponding to a most significant bit from each of the plurality of horizontal load registers into the first vertical load registers.

9. The method according to claim 7 , wherein the processing includes processing the plurality of pixels in the selected pixel window that are stored in non-sequential locations in a memory.

10. The method according to claim 7 , wherein the processing includes changing the plurality of pixels in the selected pixel windows each time the selected pixels are processed.

11. The method according to claim 7 , wherein each of the pixels correspond to a bit, and the shifted pixel in each of the horizontal load registers correspond to most significant bits of the horizontal load registers.

12. An image processing device, comprising:

a processor for processing multiple rows of pixels of an image simultaneously with a single instruction;

a plurality of horizontal load registers; and

a plurality of vertical load registers, including a first vertical load register and a second vertical load register;

wherein the multiple rows of pixels of the image are arranged in the plurality of vertical and horizontal load registers;

wherein the processor is configured to shift pixels from the first vertical load register to the second vertical load register; and

wherein the processor is further configured to shift pixels corresponding to the most significant bit of each of the plurality of horizontal load registers into the first vertical load register.

13. The image processing device according to claim 12 , wherein the processing includes processing of the multiple rows of pixels of the image that are stored in non-sequential locations in a memory.

14. The image processing device according to claim 12 , wherein the multiple rows of pixels of the image are included in a pixel window having pixel columns, and a content of the pixel window changes each time the multiple rows of pixels are processed.

15. The image processing device according to claim 12 , wherein a number of the horizontal and vertical load registers provided is based on an imaging algorithm used.

16. A method, comprising:

building a plurality of vertical and horizontal load registers to include a plurality of pixels of an image spanning across multiple rows and columns; and

simultaneously processing selected pixels of the plurality of pixels spanning across the multiple rows using a single instruction;

shifting pixels from a first vertical load register of the plurality of vertical load registers into a second vertical load register of the plurality of vertical load registers; and

shifting pixels corresponding to most significant bits of each of the plurality of horizontal load registers into the first vertical load register.

17. The image processing device according to claim 12 , wherein the number of horizontal load registers is equal to the number of pixels stored in the first vertical load register.

18. The method according to claim 1 , wherein said shifting pixels of the first vertical load register into the second vertical load register further comprises:

shifting each of the pixels of the first vertical load register into a corresponding position in the second vertical load register.

Assignments (11)