Amplitude limiting circuit
View Patent ↗An amplitude limiting value can be set to an intended value of a designer and the dependence of the amplitude limiting value on the temperature can be avoided. An amplitude limiting circuit according to the present invention includes a pair of first conductivity type MOS transistors provided in a diode-connected configuration, which is connected between one output terminal of a differential circuit and the other output terminal thereof, a first source follower circuit comprising second conductivity type first and second MOS transistors connected in series between a first power supply and a second power supply, a second source follower circuit comprising second conductivity type third and fourth MOS transistors connected in series between the first power supply and the second power supply, and a current supply circuit comprising a current source that outputs a current proportional to an absolute temperature and a resistor both of which are connected in series between the first power supply and the second power supply.
1. An amplitude limiting circuit, comprising:
a differential circuit which comprises a first transistor having a control electrode, a first electrode connected to a first node and a first output node and a second electrode connected to a second node and a second output node, a second transistor having a control electrode, a first electrode connected to the first output node and a second electrode connected to the second output node, a third transistor having a control electrode connected to a first input node, a first electrode connected to the first electrode of the second transistor and a second electrode, and a fourth transistor having a control electrode connected to a second input node, a first electrode connected to the second electrode of the second transistor and a second electrode connected to the second electrode of the third transistor;
a first source follower circuit which is connected to the first node and the control electrode of the second transistor, said first source follower circuit comprising a fifth transistor having a control electrode connected to the first node, first electrode supplied with a power supply voltage and a second electrode connected to the control electrode of the second transistor; and a first current source connected to the second electrode of the fifth transistor and supplied with a ground voltage; and
a second source follower circuit which is connected to the second node and the control electrode of the first transistor, said second source follower circuit comprising a sixth transistor having a control electrode connected to the second node, a first electrode supplied with the power supply voltage and a second electrode connected to the control electrode of the first transistor; and a second current source connected to the second electrode of the sixth transistor and supplied with the ground voltage;
wherein the differential circuit further comprises:
a third current source connected to the second electrodes of the third and fourth transistors and supplied with the ground voltage.
2. The amplitude limiting circuit according to claim 1 , wherein the first and second transistors are PMOS transistors and the third, fourth, fifth and sixth transistors are NMOS transistors.
3. An amplitude limiting circuit comprising:
a differential circuit which comprises a first transistor having a control electrode, a first electrode connected to a first node and a first output node and a second electrode connected to a second node and a second output node, a second transistor having a control electrode, a first electrode connected to the first output node and a second electrode connected to the second output node, a third transistor having a control electrode connected to a first input node, a first electrode connected to the first electrode of the second transistor and a second electrode, and a fourth transistor having a control electrode connected to a second input node, a first electrode connected to the second electrode of the second transistor and a second electrode connected to the second electrode of the third transistor;
a first source follower circuit which is connected to the first node and the control electrode of the second transistor, said first source follower circuit comprising a fifth transistor having a control electrode connected to the first node, a first electrode supplied with a power supply voltage and a second electrode connected to the control electrode of the second transistor; and a sixth transistor having a control electrode, a first electrode supplied with a ground voltage and a second electrode connected to the second electrode of the fifth transistor;
a second source follower circuit which is connected to the second node and the control electrode of the first transistor, said second source follower circuit comprising a seventh transistor having a control electrode connected to the second node, a first electrode supplied with the power supply voltage and a second electrode connected to the control electrode of the first transistor; and an eighth transistor having a control electrode connected to the control electrode of the sixth transistor, a first electrode supplied with the ground voltage and a second electrode connected to the second electrode of the seventh transistor;
a first current source connected to the control electrode of the eighth transistor and supplied with the power supply voltage; and
a resistor connected to the control electrode of the eighth transistor and supplied with the ground voltage;
wherein the differential circuit further comprises:
a second current source connected to the second electrodes of the third and fourth transistors and supplied with the ground voltage.
4. The amplitude limiting circuit according to claim 3 , wherein the first and second transistors are PMOS transistors and the third, fourth, fifth, sixth, seventh and eighth transistors are NMOS transistors.
5. An amplitude limiting circuit, comprising:
a differential circuit which comprises
a first output node;
a second output node;
a first node;
a second node connected to the second output node;
a first transistor having a control electrode, a first electrode connected to the first output node and the first node and a second electrode connected to the second node;
a second transistor having a control electrode, a first electrode connected to the first output node and a second electrode connected to the second electrode of the first transistor;
a third transistor having a control electrode connected to a first input node, a first electrode connected to the first electrode of the second transistor and a second electrode;
a fourth transistor having a control electrode connected to a second input node, a first electrode connected to the second electrode of the second transistor and a second electrode connected to the second electrode of the third transistor;
a first source follower circuit which is connected to the first node and the control electrode of the second transistor, said first source follower circuit comprising a fifth transistor having a control electrode connected to the first node, a first electrode supplied with a ground voltage and a second electrode connected to the control electrode of the second transistor; and a first current source connected to the second electrode of the fifth transistor and supplied with a power supply voltage; and
a second source follower circuit which is connected to the second node and the control electrode of the first transistor, said second source follower circuit comprising a sixth transistor having a control electrode connected to the second node, a first electrode supplied with the around voltage and a second electrode connected to the control electrode of the first transistor; and a second current source connected to the second electrode of the sixth transistor and supplied with the power supply voltage;
wherein the differential circuit further comprises:
a third current source connected to the second electrodes of the third and fourth transistors and supplied with the ground voltage.
6. The amplitude limiting circuit according to claim 5 , wherein the first, second, fifth and sixth transistors are PMOS transistors and the third and fourth transistors are NMOS transistors.