Self testing and securing ram system and method
A self-testing and correcting read only memory (RAM) device and methodology is disclosed herein. The device includes at least one array of memory to enable data storage and self-testing RAM interface for evaluating, correcting, and/or compensating for memory cell errors. The RAM device, via the self-testing RAM interface, supports interaction with a central processing unit (CPU) to facilitate testing of the CPU to memory interface as well as the device memory array. Furthermore, the subject invention provides for a system and method of securely storing data to volatile memory. More specifically, the RAM interface component can be employed to, among other things, store data in noncontiguous locations, encrypt/decrypt data as well as perform authentication checks to ensure the integrity of data and/or deter attacks thereon. All or significant portions of such functionality can be performed without burdening the CPU and affecting processing speed or efficiency.
1 . A secure volatile memory system comprising:
a CPU interface component to receive and satisfy random access memory read/write requests from a central processor; and
a security system that securely stores and retrieves data from volatile memory in response to the requests received via the interface component.
2 . The system of claim 1 , wherein the security system includes a data storage component that maps related data to memory cells in a non-linear fashion.
3 . The system of claim 2 , wherein the data storage component maps data to memory cells in accordance with a key provided by the CPU and/or operating system associated with a process context.
4 . The system of claim 2 , wherein related data is stored in non-contiguous memory cells.
5 . The system of claim 2 , wherein the data storage component includes a data location generator that generates pseudo-random locations to store related data.
6 . The system of claim 1 , wherein the security system includes an encryption component that encrypts data saved to one or more memory cells and decrypts data read from one or more memory cells.
7 . The system of claim 6 , wherein the encryption component encrypts and decrypts data with a key provided by a user.
8 . The system of claim 7 , wherein the key is provided by a smart card.
9 . The system of claim 6 , wherein the security system further comprises an authentication component that verifies that data stored to the memory was not changed from the time it was stored to the memory to the time it was read.
10 . The system of claim 9 , wherein the authentication component employs a hash function to detect changes to the data.
11 . The system of claim 10 , wherein the authentication component utilizes a redundancy check to detect changes to the data.
12 . The system of claim 1 , wherein the CPU interface component and the security system are associated with and/or executed by an interface embedded on a circuit board with one or more memory arrays.
13 . The system of claim 12 , wherein the CPU interface component and security system are executed by an interface that receives and controls one or more memory modules.
14 . The system of claim 13 , the interface includes a microprocessor.
15 . The system of claim 14 , the interface includes a memory component that facilitates execution of security protocols.
16 . The system of claim 12 , the interface is implemented with discrete logic.
17 . The system of claim 12 , the interface is implemented with SoC (System on Chip) technology.
18 . A system for securely storing volatile data comprising:
a means for receiving information including two or more of data, a read/write indicator and an address from a central processing unit;
a means for storing and retrieving information from random access memory; and
a means for securing the stored data from active and/or passive attacks.
19 . The system of claim 18 , wherein the means for securing stored data comprises storing related data in noncontiguous memory cells.
20 . The system of clam 18 , wherein the means for securing stored data comprises storing data to locations indicated by a key associated with a process context to enable interaction with stored data by contextually related processes.
21 . The system of claim 18 , wherein the means for securing stored data comprises encrypting data prior to storage and decrypting data prior to providing the data to the central processing unit.
22 . A system of secure interaction with random access memory comprising:
a CPU interface component that receives at least two of data, a read/write indicator and an address from a CPU; and
a security system that securely stores data provided by the CPU in memory, the security system comprising:
a data storage management component that identifies and stores related data portions in noncontiguous memory cells and generates a mapping of CPU provided addresses to actual storage addresses for use in retrieval of data; and
a digital rights component that includes an encryption component to encrypt/decrypt stored data.
23 . The system of claim 22 , wherein the CPU interface component and the security system are executed by a microprocessor embedded on a circuit board with one or more memory arrays.
24 . The system of claim 22 , wherein the CPU interface component and the security system are executed by a microprocessor associated with an interface that receives and manages one or more RAM memory devices comprising one or more memory arrays.
25 . The system of claim 24 , wherein the interface is further operable to test the integrity of memory cells and relocate data slated for storage in a defective cell to another memory cell.
26 . A method for securely storing data in random access memory comprising:
receiving one or more blocks of data from a central processing unit for storage in random access memory; and
determining a location in memory to store each data block, the locations of related data blocks being non-contiguous.
27 . A method of claim 26 , further comprising populating a map including an address specified by the central processing unit and the actual storage address determined.
28 . A method of claim 27 , further comprising storing the data blocks to determined memory locations.
29 . The method of claim 27 , further comprising encrypting the data blocks prior to saving to memory.
30 . The method of claim 29 , wherein the data blocks are encrypted utilizing symmetric key encryption, the authorized user having the only key to decrypt the data blocks.
31 . The method of claim 30 , wherein the key is stored on a smart card.
32 . The method of claim 26 , wherein determining a location in memory comprises generating an address in accordance with an algorithm and/or pattern associated with a process context key provided by the CPU or operating system, the key limiting access to memory read/write functionality to processes with the same context.
33 . A computer readable medium having stored thereon computer executable instructions for carrying out the method of claim 26 .
34 . A method for retrieving data from random access memory comprising:
receiving a request for data from one or more specific addresses from a central processing unit;
determining a storage address from a mapping utilizing the received address from the CPU; and
retrieving the data from memory utilizing the storage address.
35 . The method of claim 34 , further comprising retrieving a key to decrypt the retrieved data.
36 . The method of claim 34 , further comprising authenticating the retrieved data to determine whether the data has been corrupted.
37 . The method of claim 36 , further comprising generating an error if the data has been corrupted.
38 . The method of claim 36 , further comprising employing error correction techniques to correct corrupted data.
39 . The method of claim 34 , further comprising providing the retrieved data to the central processor.
40 . A computer readable medium having stored thereon computer executable instructions for carrying out the method of claim 34.