Data de-scrambler
View Patent ↗A method and apparatus are disclosed for efficiently de-scrambling one or more bytes of data according to DSL standards on a processor. This is achieved by providing an instruction for de-scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to de-scramble data with a single instruction thus allowing for more efficient and faster de-scrambling operations for subsequent processing.
1. A method comprising:
providing a processor with a single instruction including
an opcode indicating a de-scrambling instruction,
an input data value using a first field of the de-scrambling instruction,
an input state value using a second field of the de-scrambling instruction, wherein a plurality of bits of the input data value from one application of the de-scrambling instruction is the input state value for a next application of the de-scrambling instruction, and
a reference to a destination register of the processor using a third field of the de-scrambling instruction;
de-scrambling, using the processor, the input data value using the input state value to create a de-scrambled output value; and
storing the de-scrambled output value in the destination register.
2. The method of claim 1 , wherein the input data value is de-scrambled in accordance with Digital Subscriber Line (DSL) standards.
3. The method of claim 1 , wherein the input data value is 64 bits of scrambled source data.
4. The method of claim 1 , wherein the de-scrambled output value is a 64-bit output.
5. The method of claim 3 , wherein the last 23 bits of the 64-bit input data value from one application of the de-scrambling instruction is the input state value for a next application of the de-scrambling instruction.
6. The method of claim 1 , wherein the method is used in a central-office modem end of a Digital Subscriber Line (DSL) link.
7. A method comprising:
de-scrambling data using a processor, comprising:
receiving an instruction including
an opcode indicating a de-scrambling instruction,
a first field relating to an input data value, and
a second field relating to an input state value, wherein a plurality of bits of the input data value from one application of the de-scrambling instruction is the input state value for a next application of the de-scrambling instruction, and
de-scrambling the input data value using the input state value to create a de-scrambled output value.
8. The method of claim 7 , wherein the input data value includes 64 bits of scrambled source data and the input state value includes 23 bits of previous de-scrambling state data.
9. The method of claim 8 , wherein the last 23 bits of the 64 bits of scrambled source data for one application of the de-scrambling instruction is the previous de-scrambling state data for a next application of the de-scrambling instruction.
10. The method of claim 7 , wherein the data is Digital Subscriber Line (DSL) data and the DSL data is de-scrambled according to Asymmetric Digital Subscriber (ADSL) or Very High Bit-Rate DSL (VDSL) standards.
11. The method of claim 7 , wherein the processor is a 64-bit long instruction word machine comprising two identical execution units.
12. The method of claim 7 , wherein the processor is used in a chip-set implementing a central-office modem end of a Digital Subscriber Line (DSL) link.
13. The method of claim 7 , wherein 8 bytes of data are de-scrambled in a single cycle.
14. A processor comprising:
a plurality of registers; and
at least one execution unit configured to de-scramble data by:
receiving an instruction including
an opcode indicating a de-scrambling instruction,
a first field relating to an input data value, and
a second field relating to an input state value, wherein a plurality of bits of the input data value from one application of the de-scrambling instruction is the input state value for a next application of the de-scrambling instruction, and
de-scrambling the input data value using the input state value to create a de-scrambled output value.
15. The processor of claim 14 , wherein the input data value includes 64 bits of scrambled source data and the input state value includes 23 bits of previous de-scrambling state data.
16. The processor of claim 15 , wherein the last 23 bits of the 64 bits of scrambled source data for one application of the de-scrambling instruction is the previous de-scrambling state data for a next application of the de-scrambling instruction.
17. The processor of claim 14 , wherein the data is Digital Subscriber Line (DSL) data and the DSL data is de-scrambled according to Asymmetric Digital Subscriber (ADSL) or Very High Bit-Rate DSL (VDSL) standards.
18. The processor of claim 14 , wherein the processor is a 64-bit long instruction word machine comprising two identical execution units.
19. The processor of claim 14 , wherein the processor is used in a chip-set implementing a central-office modem end of a Digital Subscriber Line (DSL) link.
20. The processor of claim 14 , wherein 8 bytes of data are de-scrambled in a single cycle.
21. An apparatus comprising:
a processor;
a plurality of registers accessible to the processor; and
means for de-scrambling by:
receiving an instruction including
an opcode indicating a de-scrambling instruction,
a first field relating to an input data value, and
a second field relating to an input state value, wherein a plurality of bits of the input data value from one application of the de-scrambling instruction is the input state value for a next application of the de-scrambling instruction, and
de-scrambling the input data value using the input state value to create a de-scrambled output value.
22. The apparatus of claim 21 , wherein input data value includes 64 bits of scrambled source data and the input state value includes 23 bits of previous de-scrambling state data.
23. The apparatus of claim 22 , wherein the last 23 bits of the 64 bits of scrambled source data for one application of the de-scrambling instruction is the previous de-scrambling state data for a next application of the de-scrambling instruction.
24. The apparatus of claim 21 wherein the data is Digital Subscriber Line (DSL) data and the DSL data is de-scrambled according to Asymmetric Digital Subscriber (ADSL) or Very High Bit-Rate DSL (VDSL) standards.
25. The apparatus of claim 21 , wherein the processor is a 64-bit long instruction word machine comprising two identical execution units.
26. The apparatus of claim 21 , wherein the processor is used in a chip-set implementing a central-office modem end of a Digital Subscriber Line (DSL) link.
27. The apparatus of claim 21 , wherein 8 bytes of data are de-scrambled in a single cycle.
28. A computer readable storage medium having computer program code recorded thereon, that when executed by a processor, causes the processor to de-scramble scrambled data, by:
receiving an instruction including
an opcode indicating a de-scrambling instruction,
a first field relating to an input data value, and
a second field relating to an input state value, wherein a plurality of bits of the input data value from one application of the de-scrambling instruction is the input state value for a next application of the de-scrambling instruction, and
de-scrambling the input data value using the input state value to create a de-scrambled output value.