Method for providing zero overhead looping using carry chain masking
View Patent ↗A method for reducing overhead on a loop of a plurality of instructions is disclosed. The method includes providing a carry mask, the carry mask having a first value for the loop being performed at least the particular number of times minus one and a second value for at least a last instruction of the loop being performed a last time, providing addition logic, wherein the carry mask and a current instruction address of the plurality of instructions correspond to inputs of the addition logic and determining which of the plurality of instructions is to be executed using the carry mask to provide a resultant of the addition logic based on the carry mask and the current instruction address of the plurality of instructions.
1. A method for reducing overhead on a loop of a plurality of instructions, the loop being performed a particular number of times, the method comprising:
providing a carry mask, the carry mask having a first value for the loop being performed at least the particular number of times minus one and a second value for at least a last instruction of the loop being performed a last time;
providing addition logic, wherein the carry mask and a current instruction address of the plurality of instructions correspond to inputs of the addition logic; and
determining which of the plurality of instructions is to be executed using the carry mask to provide a resultant of the addition logic based on the carry mask and the current instruction address of the plurality of instructions by performing the operation A n XOR i n XOR (C n AND M n ), where A n is a n th bit of the current instruction address, i n is one for a least significant bit of the address of the current instuction and zero otherwise, C n is a carry bit for a n th digit of the carry mask and M n is a n th digit of the carry mask, the resultant of the addition logic corresponding to a next instruction of the plurality of instructions if the current instruction is not a last instruction, the resultant of the addition logic corresponding to an address of a first instruction if the current instruction is not a last instruction, the resultant of the addition logic corresponding to an address of a first instruction if the current instruction address is the last instruction and the loop being performed less than the particular number of times.
2. The method of claim 1 wherein each of the plurality of instructions has an address.
3. The method of claim 2 wherein the determining step provides the resultant of the addition logic using the carry mask and the address of the current instruction.
4. The method of claim 3 wherein the first value of the carry mask includes at least one one and at least one zero, the at least one zero in each of a first portion of a plurality of bit positions higher than or equal to a most significant bit of the address of the last instruction and the at least one one in each of a second portion of the plurality of bit positions less than the most significant bit of the address of the last instruction.
5. The method of claim 3 wherein the second value of the carry mask includes the at least one one in each of the plurality of bit positions.
6. The method of claim 5 wherein the determining steps performs the address of the current instruction XOR one XOR (the carry mask AND a carry).
7. The method of claim 1 wherein the plurality of instructions includes a number of instructions, the number of instruction being equal to a power of two.
8. The method of claim 1 further comprising:
storing a count of a number of times the loop has been performed.
9. The method of claim 1 wherein the address of the current instruction of the plurality of instructions corresponds to one of the current instruction of the plurality of instructions corresponds to one of the inputs of the addition logic, the addition logic using the address of the current instruction to determine which of the plurality of instructions is to be executed.