Method for making thin film transistors with lightly doped regions
View Patent ↗A method for making a thin film transistor (TFT) with a lightly doped region. The process of the invention is compatible with the currently common TFT manufacturing processes. A substrate with a photoresist layer thereon is subjected to two-step exposure with different exposure energies to form a full-through pattern and a non-through pattern after development. The same photoresist layer is subjected to two etching steps to form a gate region and an intra-gate region. The gate region and the intra-gate region are respectively doped with different dopant concentrations. Therefore, the number of times forming and exposing the photoresist layer is reduced.
1. A method for making a thin film transistor with lightly doped regions, comprising:
providing a substrate with a semiconductor material layer;
forming an insulation layer over the semiconductor material layer;
forming a conductive layer over the insulation layer;
forming a photoresist layer over the conductive layer;
applying a first exposure energy to the photoresist layer to form a first exposed region;
applying a second exposure energy to the photoresist layer to form a second exposed region, wherein the first exposure energy is different from the second exposure energy;
performing a development process on the photoresist layer to form a full-through pattern and a non-through pattern;
etching a first portion of the conductive layer exposed through the full-through pattern and the gate insulation layer underneath the first portion of the conductive layer, and thereby exposing a source and a drain region in the semiconductor material layer to be formed;
doping the source region and the drain region of the semiconductor material layer at high dopant concentration to form a source and a drain;
removing the non-through pattern to expose a second portion of the conductive layer;
etching the exposed second portion of the conductive layer to expose a lightly doped region; and
lightly doping in the lightly doped region of the conductive layer.
2. The method for making a thin film transistor with lightly doped regions of claim 1 , wherein the gate is a duel gate.
3. The method for making a thin film transistor with lightly doped regions of claim 1 , wherein the lightly doped region is an intra-gate region.
4. The method for making a thin film transistor with lightly doped regions of claim 1 , wherein the lightly doped region is a lightly doped drain region.
5. The method for making a thin film transistor with lightly doped regions of claim 1 , wherein the thickness of the insulation layer is in a range of 200 to 2000 angstroms.
6. The method for making a thin film transistor with lightly doped regions of claim 1 , wherein the step of removing the non-through pattern of the photoresist layer is achieved by ashing the photoresist layer by using oxygen plasma.
7. The method for making a thin film transistor with lightly doped regions of claim 1 , wherein a buffer layer is further formed between the substrate and the semiconductor material layer.
8. The method for making a thin film transistor with lightly doped regions of claim 1 , wherein the semiconductor material layer is a polysilicon layer.
9. A method for making a thin film transistor with lightly doped regions, comprising:
providing a substrate with a semiconductor material layer, wherein the semiconductor material layer includes a source region and a drain region;
forming an insulation layer over the semiconductor material layer;
forming a conductive layer over the insulation layer;
forming a photoresist layer over the conductive layer;
applying a first exposure energy and a second exposure energy to the photoresist layer at the same time to form a first exposed region and a second exposed region, wherein the first exposure energy is different from the second exposure energy;
performing a development process on the photoresist layer to form a full-through pattern and a non-through pattern;
etching a first portion of the conductive layer exposed through the full-through pattern and the gate insulation layer underneath the first portion of the conductive layer;
doping the source region and the drain region of the semiconductor material layer at high dopant concentration to form a source and a drain;
removing the non-through pattern to expose a second portion of the conductive layer;
etching the exposed second portion of the conductive layer to expose a lightly doped region; and
lightly doping in the lightly doped region of the conductive layer.
10. The method for making a thin film transistor with lightly doped regions of claim 9 , wherein the gate is a duel gate.
11. The method for making a thin film transistor with lightly doped regions of claim 9 , wherein the lightly doped region is an intra-gate region.
12. The method for making a thin film transistor with lightly doped regions of claim 9 , wherein the lightly doped region is a lightly doped drain (LDD) region.
13. The method for making a thin film transistor with lightly doped regions of claim 9 , wherein the thickness of the insulation layer is in a range of 200 to 2000 angstroms.
14. The method for making a thin film transistor with lightly doped regions of claim 9 , wherein the first and second exposure energies are generated by means by allowing a light source travel through a phase-shift mask.
15. The method for making a thin film transistor with lightly doped regions of claim 9 , wherein the step of removing the non-through pattern of the photoresist layer is achieved by ashing the photoresist layer by using oxygen plasma.
16. The method for making a thin film transistor with lightly doped regions of claim 9 , wherein a buffer layer is further formed between the substrate and the semiconductor material layer.
17. The method for making a thin film transistor with lightly doped regions of claim 9 , wherein the semiconductor material layer is a polysilicon layer.