Method of manufacturing semiconductor device and semiconductor device

1. A method for manufacturing a semiconductor device, the device comprising MOSFET structure having an F-containing NiSi layer formed on diffusion regions and on gate electrodes, a depth from the bottom of the F-containing NiSi layer to the junction position of the diffusion regions being confined within the range of 20 to 100 nm, the method comprising:

forming the gate electrodes above a semiconductor substrate with a gate insulation film being interposed between the semiconductor substrate and the gate electrodes;

forming the diffusion regions by introducing an impurity into the semiconductor substrate with the gate insulating film and the gate electrodes being employed as a mask;

forming a F-containing layer on a surface layer of a silicide-forming region by ion-implanting F atoms at a dosage of 8.0×10 13 cm −2 or more in the silicide-forming region of silicon for forming the silicide;

depositing a Ni film on the F-containing layer without heat-treating the F-containing layer;

heat-treating the Ni film to turn the silicon of the silicide-forming region into NiSi, thereby forming the F-containing NiSi layer on diffusion regions and on gate electrodes; and

subjecting the F-containing NiSi layer to a heat treatment for a period of time equal to or shorter than, an allowable duration defined as a function of junction depth and temperature by the following formula (A):

t a =Dj 2 /Exp(34.7−2.35×10 4 /Ta )+68  (A)

(wherein t a is the allowable duration (minutes); Dj is a depth (nm) of the position of junction as measured from the bottom of the NiSi layer; and Ta is a heat treatment temperature (K: Kelvin)).

2. The method according to claim 1 , wherein the silicide-forming region is a surface layer of the diffusion region and of the gate electrode.

3. The method according to claim 1 , wherein the silicide-forming region is an additional silicon layer formed on the diffusion region and on the gate electrode.

4. The method according to claim 1 , wherein the additional silicon layer is formed by a process comprising:

forming a silicon film above the entire surface of the semiconductor substrate by chemical vapor-phase deposition subsequent to the formation of the diffusion region and prior to the F implantation;

selectively turning surfaces of the silicon film horizontal to the semiconductor substrate into a carbon-containing silicon layer;

thermally oxidizing the silicon film including the carbon-containing silicon layer; and

dipping the thermally oxidized silicon film in a hydrogen fluoride solution and selectively removing the silicon film existing on a vertical plane of the semiconductor substrate to leave the carbon-containing silicon layer selectively on the horizontal plane of the semiconductor substrate.

5. The method according to claim 3 , wherein the bottom of the F-containing NiSi layer located on the diffusion regions is positioned flush with or higher than a main surface of the semiconductor substrate.

6. The method according to claim 1 , wherein the ion implantation is performed within the range of not more than film thickness of the silicon that can be consumed by the silicide-forming reaction.

7. The method according to claim 1 , further comprising depositing a silicon nitride layer on the F-containing NiSi layer.

8. The method according to claim 7 , further comprising:

depositing an insulating film on the silicon nitride layer; and

forming a contact hole in the insulating film by RIE using the silicon nitride layer as an etching stopper.

9. The method according to claim 1 , further comprising:

depositing a metal film on the F-containing NiSi layer; and

heating the semiconductor substrate having the metal film formed thereon at a temperature of 450° C. or more for a period of time, an allowable duration defined as a function of junction depth and temperature by the following formula (A):

t a =Dj 2 /Exp(34.7−2.35×10 4 /Ta )+68  (A)

(wherein t a is the allowable duration (minutes); Dj is the depth (nm) of the position of junction as measured from the bottom of the NiSi layer; and Ta is a heat treatment temperature (K: Kelvin)).

10. The method according to claim 9 , wherein the metal includes Ti.