Load drive circuit and display device using the same

1. A load drive circuit comprising:

a first N-channel MOS field effect transistor having a source directly connected to a first reference potential point, the first N-channel MOS field effect transistor inversely amplifying a signal, which is inputted to a gate and outputted from a drain, for driving a load;

a first current source directly connected to the gate and being capable of controlling current output; and

a first switch circuit directly connected between the gate and the first reference potential point, wherein

the current source is configured to supply a current from the first current source to the gate in order to control a transition time during which an output voltage of the drain falls.

2. The load drive circuit according to claim 1 , further comprising a first P-channel MOS field effect transistor having a drain connected to the drain of said first N-channel MOS field effect transistor, and a source connected to a first positive potential point.

3. The load drive circuit according to claim 2 , wherein said first current source includes a second P-channel MOS field effect transistor having the drain connected to the gate of said first N-channel MOS field effect transistor, and the source connected to a second positive potential point.

4. The load drive circuit according to claim 3 , wherein said first current source further comprises a Zener diode connected between the gate of said second P-channel MOS field effect transistor and said second positive potential point.

5. The load drive circuit according to claim 3 , wherein said first current source further comprises a third P-channel MOS field effect transistor having the gate connected to its own drain and the gate of said second P-channel MOS field effect transistor, having the drain connected at least through a switch circuit to said first reference potential point, and having the source connected to the second positive potential point.

6. The load drive circuit according to claim 2 , further comprising:

a second N-channel MOS field effect transistor having the gate connected to the gate of said first P-channel MOS field effect transistor and having the source connected to the first reference potential point; and

a second switch circuit connected between the gate of said first P-channel MOS field effect transistor and a second reference potential point.

7. The load drive circuit according to claim 1 , wherein said first current source comprises a drive element capable of outputting an output saturation current in order to drive said first N-channel MOS field effect transistor.

8. The load drive circuit according to claim 1 , wherein said first current source is configured by using a drive element capable of applying the drive voltage as being suppressed under the maximum drive voltage.

9. The load drive circuit according to claim 1 , wherein said first current source uses a current mirror circuit.

10. The load drive circuit according to claim 1 , further comprising a feedback capacitor additionally connected in parallel with a parasitic capacitance between the gate and the drain of said first N-channel MOS field effect transistor.

11. The load drive circuit according to claim 1 , wherein a second positive potential point is connected through an electrostatic capacitance and a second switch circuit to the gate of said first N-channel MOS field effect transistor.

12. The load drive circuit according to claim 1 , further comprising a second switch circuit connected between the gate of said first N-channel MOS field effect transistor and a second positive potential point.

13. The load drive circuit according to claim 1 , further comprising:

a second N-channel MOS field effect transistor inversely amplifying a signal that is inputted to a gate and outputted from a drain;

a second current source connected to the gate of the second N-channel MOS field effect transistor and being capable of controlling current output; and

a second switch circuit connected between the gate of the second N-channel MOS field effect transistor and a second reference potential point,

wherein the gate of the first N-channel MOS field effect transistor and the drain of said second N-channel MOS field effect transistor are connected with each other.

14. The load drive circuit according to claim 1 , wherein said first switch circuit is connected to the gate of the second N-channel MOS field effect transistor via a unidirectional conductive element.

15. The load drive circuit according to claim 1 , wherein said first N-channel MOS field effect transistor is connected to said first reference potential point, and is driven while making a reference to said first reference potential point.

16. The load drive circuit according to claim 1 , comprising a plurality of assemblies of said first N-channel MOS field effect transistor, said first current source and said first switch circuit for the purpose of driving a plurality of loads, and being configured so that said plurality of assemblies are integrated and united into a single circuit.

17. The load drive circuit according to claim 1 , wherein said load is a capacitive load.

18. The load drive circuit according to claim 1 , wherein the load drive circuit is configured to drive a display electrode on a flat-type display panel.

19. The load drive circuit according to claim 1 , wherein the load drive circuit is configured to drive a display electrode on a plasma display panel.

20. A load drive circuit, comprising:

a P-channel MOS field effect transistor having a source directly connected to a reference potential point, the P-channel MOS field effect transistor inversely amplifying a signal, which is inputted to a gate and outputted from a drain, for driving a load;

a current source directly connected to the gate and being capable of controlling current output; and

a switch circuit directly connected between the gate and the reference potential point, wherein

the current source is configured to supply a current from the current source to the gate in order to control a transition time during which an output voltage of the drain falls.