Circuit board having an overlapping via
View Patent ↗A printed circuit board ( 100 ) includes a first BGA landing pad ( 102 ) having a first clearance zone ( 106 ) and a second BGA landing pad ( 104 ) having a second clearance zone ( 108 ). A via ( 110 ), overlaps the first clearance zone and the second clearance zone such that the first BGA landing pad and the second BGA landing pad are electrically coupled to the via.
1. A printed circuit board, comprising:
a first BGA landing pad having a first clearance zone;
a second BGA landing pad having a second clearance zone;
a via, wherein the via overlaps the first clearance zone and the second clearance zone such that the first BGA landing pad and the second BGA landing pad are electrically coupled to the via; and
a packaged chip, wherein the printed circuit board is coupled for receiving the packaged chip, wherein the packaged chip comprises a plurality of package terminals, and wherein at least two of the package terminals are coupled to interface with the first BGA landing pad and the second BGA landing pad respectively.
2. The printed circuit board of claim 1 , wherein the at least two of the package terminals are each a package ball coupled to interface with the first BGA landing pad and the second BGA landing pad respectively.
3. The system, comprising:
a printed circuit board having a surface;
a first BGA landing pad having a first clearance zone;
a second BGA landing pad having a second clearance zone, wherein the first BGA landing pad and the second BGA landing pad are disposed on the surface of the printed circuit board;
a via, wherein the via overlaps the first clearance zone and the second clearance zone such that the first BGA landing pad and the second BGA landing pad are electrically coupled to the via; and
a packaged chip, wherein the printed circuit board is coupled for receiving the packaged chip, wherein the packaged chip comprises a plurality of package terminals, and wherein at least two of the package terminals are coupled to interface with the first BGA landing pad and the second BGA landing pad respectively.
4. The system of claim 3 , wherein the at least two of the package terminals are each a package ball coupled to interface with the first BGA landing pad and the second BGA landing pad respectively.
5. A method, comprising:
providing a printed circuit board having a surface;
disposing a first BGA landing pad having a first clearance zone on the surface;
disposing a second BGA landing pad having a second clearance zone on the surface;
disposing a via, wherein the via overlaps the first clearance zone and the second clearance zone such that the first BGA landing pad and the second BGA landing pad are electrically coupled to the via; and
providing a packaged chip, wherein the printed circuit board is coupled for receiving the packaged chip, wherein the packaged chip comprises a plurality of package terminals, and wherein at least two of the package terminals are coupled to interface with the first BGA landing pad and the second BGA landing pad respectively.
6. The method of claim 5 , wherein the at least two of the package terminals are each a package ball coupled to interface with the first BGA landing pad and the second BGA landing pad respectively.