Systems and methods for equalization of received signals in a wireless communication network
View Patent ↗An equalizer comprises a hard decision block which feeds an FEC block and a shift register, which uses past estimates during a first iteration. The output of the FEC block is fed back to the shift register during a subsequent iteration to fully remove any inter chip interference.
1. A receiver, comprising:
a serial to parallel converter configured to receive a serial data stream and convert it into a plurality of parallel data streams;
a plurality of matched filters coupled with the serial to parallel converter, the plurality of matched filters configured to match each of the parallel data streams;
a combiner configured to combine the matched parallel data streams; and
an equalizer coupled to the combiner, the equalizer comprising:
a hard decision estimation block configured to generate a hard decision estimate of input sample;
a past decision block configured to multiply past decision estimates with associated coefficients;
a future decision block configured to multiply future decision estimates with associated coefficients; and
a forward error correction block coupled with the equalizer, wherein the hard decision estimate is fed to a forward error correction block and the future decision block is fed by the forward error correction block;
wherein the forward error correction block is configured to detect errors in the hard decision estimate produced by the hard decision estimation block, and wherein the forward error correction block is further configured to only feed data back to the future estimation block if errors are detected.