Low-power consumption semiconductor memory device
View Patent ↗A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.
1. A semiconductor memory device, comprising:
a plurality of first bit lines extending in a column direction;
a plurality of second bit lines extending in said column direction alternately with said plurality of first bit lines, adjacent first and second bit lines making a bit-line set;
active regions each extending in the column direction under the first and second bit lines of each bit-line set so as to align with a corresponding bit-line set of first and second bit lines as viewed two-dimensionally, active regions adjacent in a row direction being isolated from each other by an isolation region extending in the column direction, each active region provided to form a transistor;
a plurality of first word lines extending in the row direction;
a plurality of second word lines extending in the row direction alternately with said plurality of first word lines, adjacent first and second word lines making a word-line set;
capacitor each provided in a region between and under the first and second word lines of each word-line set, said capacitors arranged being aligned in the row and column directions;
a plurality of first bit-line contacts, provided for the respective first bit lines so as to align in said row direction, each for making an electrical contact between a corresponding first bit line and a corresponding active region, said plurality of first bit-line contacts being located at prescribed intervals along the column direction; and
a plurality of second bit-line contacts, provided for the respective second bit lines so as to align in said row direction, each for making an electrical contact between a corresponding second bit line and a corresponding active region, said plurality of second bit-line contacts being located corresponding to said first bit-line contacts at said prescribed intervals along the column direction, each of said second bit-line contacts being located opposite to a corresponding first bit-line contact with respect to a corresponding one of capacitor contacts between said capacitors and said active regions, and the first and second bit-line contacts being arranged sandwiching the first and second word lines making the word-line set.
2. The semiconductor memory device according to claim 1 , wherein the first bit lines and the first word lines are selected in accordance with an access request supplied through a first port and the second bit lines and the second word lines are selected in accordance an access request supplied through a second port different from the first port.
3. The semiconductor memory device according to claim 1 , wherein the first bit line and the second bit line in the bit-line set receive data of a same attribute when selected, said attribute indicating true or complement of data.
4. The semiconductor memory device according to claim 1 , wherein adjacent two first bit lines form a bit line pair receiving complementary data when a first word line is selected, and adjacent two second bit lines form a bit line pair receiving complementary data when a second word line is selected.