IP Library › Patent Application 10949418
Patent Application
App. No. 10/949,418

Method of controlling the operation of non-volatile semiconductor memory chips

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Quick Facts
Patent No.
US None
App. No.
10/949,418
Abstract

Disclosed herewith is a method for controlling the operation of non-volatile semiconductor chips with high sequential access performance realized by smoothing out the variation of the times for writing, erasing, and reading data in/from memory cells among sectors in each of the chips.

Claims (25)

1 - 13 . (cancelled)

14 . A semiconductor memory device comprising:

a controller; and

a plurality of non-volatile semiconductor memories;

wherein said controller inputs the write command to said plurality of non-volatile semiconductor memories simultaneously in the case of the writing of the first round to said plurality of non-volatile semiconductor memories; and

wherein said controller inputs the write command to said plurality of non-volatile semiconductor memories individually in the case of the writing after the second round to said plurality of non-volatile semiconductor memories.

15 . A semiconductor memory device according to claim 14 ,

wherein said controller inputs the address to said plurality of non-volatile semiconductor memories simultaneously in the case of the writing of the first round to said plurality of non-volatile semiconductor memories, and

wherein said controller inputs the address to said plurality of non-volatile semiconductor memories individually in the case of the writing after the second round to said plurality of non-volatile semiconductor memories.

16 . A semiconductor memory device comprising:

a controller; and

a plurality of non-volatile semiconductor memories,

wherein said controller inputs the read command to said plurality of non-volatile semiconductor memories simultaneously in the case of the reading of the first round from said plurality of non-volatile semiconductor memories, and

wherein said controller inputs the read command to said plurality of non-volatile semiconductor memories individually in the case of the reading after the second round from said plurality of non-volatile semiconductor memories.

17 . A semiconductor memory device according to claim 16 ,

wherein said controller inputs the address to said plurality of non-volatile semiconductor memories simultaneously in the case of the reading of the first round from said plurality of non-volatile semiconductor memories, and

wherein said controller inputs the address to said plurality of non-volatile semiconductor memories individually in the case of the reading after the second round from said plurality of non-volatile semiconductor memories.

18 . A semiconductor memory device comprising:

a controller; and

a plurality of non-volatile semiconductor memories,

wherein said controller inputs the erase command to said plurality of non-volatile semiconductor memories simultaneously in the case of the erasing of the first round to said plurality of non-volatile semiconductor memories; and

wherein said controller inputs the erase command to said plurality of non-volatile semiconductor memories individually in the case of the erasing after the second round to said plurality of non-volatile semiconductor memories.

19 . A semiconductor memory device according to claim 18 ,

wherein said controller inputs the address to said plurality of non-volatile semiconductor memories simultaneously in the case of the erasing of the first round to said plurality of non-volatile semiconductor memories; and

wherein said controller inputs the address to said plurality of non-volatile semiconductor memories individually in the case of the erasing after the second round to said plurality of non-volatile semiconductor memories.