Sleep mode recovery
View Patent ↗One embodiment in accordance with the invention is a circuit. For example, the circuit can include a first stage amplifier coupled to receive a reference voltage. The circuit can also include a second stage amplifier coupled with an output of the circuit and the first stage amplifier. Note that the output can be fed back to the first stage amplifier. Additionally, the circuit can include a module coupled with the second stage amplifier and can restrict current flow to the second stage amplifier and the output provided the circuit is in a sleep mode. Furthermore, the module can drive a terminal of the second stage amplifier to a logic low voltage provided the circuit is in the sleep mode.
1. A circuit comprising:
a first stage amplifier coupled to receive a reference voltage;
a second stage amplifier coupled with an output of said circuit and said first stage amplifier, said output fed back to said first stage amplifier; and
a module coupled with said second stage amplifier and for restricting current flow to said second stage amplifier and said output provided said circuit is in a sleep mode, said module for driving a terminal of said second stage amplifier to a logic low voltage provided said circuit is in said sleep mode.
2. The circuit of claim 1 , wherein said module for selectively coupling a voltage supply to said second stage amplifier and said output provided said sleep mode is disabled.
3. The circuit of claim 2 , wherein said first stage amplifier is “jump started” upon receiving said voltage supply, provided said sleep mode is disabled.
4. The circuit of claim 1 , wherein said module comprises a switching element coupled with said terminal of said second stage amplifier.
5. The circuit of claim 4 , wherein said switching element is coupled with ground.
6. The circuit of claim 1 , wherein said module comprises a switching element coupled with a second terminal of said second stage amplifier.
7. The circuit of claim 6 , wherein said switching element is coupled with a voltage source.
8. A method comprising:
pulling a terminal of a second stage amplifier to a logic low voltage provided a sleep mode is invoked;
restricting current flow to said second stage amplifier and a circuit output provided said sleep mode is invoked;
driving said circuit output towards a voltage source provided said sleep mode is disabled; and
feeding voltage at said output to a first stage amplifier provided said sleep mode is disabled, said first stage amplifier coupled with said second stage amplifier.
9. The method as described in claim 8 , wherein said pulling performed by a switching element coupled with ground.
10. The method as described in claim 9 , wherein said restricting performed by a second switching element coupled with said voltage source, said second switching element coupled with said switching element.
11. The method as described in claim 8 , wherein said restricting performed by a switching element coupled with said voltage source.
12. The method as described in claim 8 , wherein said circuit is an amplifier circuit.
13. The method as described in claim 8 , wherein said second stage amplifier comprises a transistor.
14. The method as described in claim 8 , wherein said first stage amplifier comprises a transistor coupled to receive a voltage reference signal.
15. A circuit comprising:
means for discharging a terminal of a second stage amplifier to a logic low voltage provided a sleep mode is invoked;
means for preventing current flow to said second stage amplifier and an output of said circuit provided said sleep mode is invoked;
means for driving said output towards a voltage supply provided said sleep mode is disabled; and
means for feeding voltage at said output to a first stage amplifier provided said sleep mode is disabled, said first stage amplifier coupled with said second stage amplifier.
16. The circuit of claim 15 , wherein said means for discharging comprises a switching element coupled with ground.
17. The circuit of claim 16 , wherein said means for restricting comprises a second switching element coupled with a voltage source, said second switching element coupled with said switching element.
18. The circuit of claim 15 , wherein said means for restricting comprises a switching element coupled with a voltage source.
19. The circuit of claim 15 , wherein said second stage amplifier comprises a transistor.
20. The circuit of claim 15 , wherein said first stage amplifier comprises a transistor coupled to receive a reference voltage signal.