Electroluminescent devices and displays with integrally fabricated address and logic devices fabricated by printing or weaving
View Patent ↗Improved electroluminescent and photonic devices with integrated logic and control circuits are disclosed. Low mobility, contact barrier, space charge limitation and carrier balancing are provided solutions that increase efficiency, reliability and longevity of the devices. Device power loss and power requirements are reduced. True-ohmic contact materials allow a gate-controlled, light emitting organic triode MESFET configuration that eliminates commonly used ITO thereby increasing luminous output, and providing ease of address and control by integrally fabricated complementary MESFET address and control circuitry. The devices can be fabricated by printing or by weaving appropriate materials, and can be configured as color displays.
1. An OMESFET comprising:
(a) a substrate;
(b) an organic semiconductor contacting said substrate;
(c) a first true-ohmic contact metal contacting said semiconductor and at a first edge of said semiconductor;
(d) a source interconnect metal contacting said first true-ohmic contact metal;
(e) a second true-ohmic contact metal contacting said semiconductor at a second edge of said semiconductor opposite said first edge;
(f) a drain interconnect metal contacting said second true-ohmic contact metal;
(g) a high barrier surround gate contacting said semiconductor between said first true-ohmic contact metal and said second true-ohmic contact metal; and
(h) a gate interconnect metal contacting said semiconductor and said high barrier surround gate.
2. The OMESFET of claim 1 wherein said high barrier surround gate is equidistant between said first true-ohmic contact metal and said second true-ohmic contact metal.
3. The OMESFET of claim 1 wherein said high barrier surround gate is spaced 3000 nm or less from said first-ohmic contact metal.
4. The OMESFET of claim 1 wherein said high barrier surround gate is positioned at a distance from said first true-ohmic contact metal to tune carrier balance.
5. The OMESFET of claim 1 wherein a first portion of said OMESFET is formed by depositing upon said substrate said semiconductor and subsequently printing said first true-ohmic contact metal and said second true-ohmic contact metal and said high barrier surround gate in pattern and sequence required to produce cooperative elements of said OMESFET.
6. The OMESFET of claim 5 wherein said source interconnect metal and said gate interconnect metal and said drain interconnect metal are subsequently printed upon said first portion forming a second portion of said OMESFET.
7. The OMESFET of claim 6 wherein said first and said second portions are encapsulated to all components of said OMESFET from oxygen.
8. The OMESFET of claim 1 wherein said semiconductor and said first true-ohmic contact metal and said second true-ohmic contact metal and said high barrier surround gate and said source interconnect metal and said gate interconnect metal and said drain interconnect metal are formed into fibers and said fibers are organized in a warp and a woof of a weaving loom and are woven thereby forming a weave to fabricate said OMESFET.
9. The OMESFET of claim 8 wherein said weave is subsequently attached to said substrate.
10. A method for fabricating an OMESFET comprising:
(a) providing a substrate;
(b) affixing a semiconductor to said substrate;
(c) affixing a first true-ohmic contact metal to a first edge of said semiconductor;
(d) contacting said first true-ohmic contact metal with a source interconnect metal;
(e) affixing a second true-ohmic contact to a second edge of said semiconductor and opposite said first edge;
(f) contacting said second true-ohmic contact metal with a drain interconnect metal;
(g) affixing a high barrier surround gate to said semiconductor between said first true-ohmic contact metal and said second true-ohmic contact metal; and
(h) contacting said semiconductor and said high barrier surround gate with a gate interconnect metal.
11. The method of claim 10 wherein said high barrier surround gate is spaced 3000 nm or less from said first true-ohmic contact metal.
12. The method of claim 10 comprising the additional step of encapsulating all components of said OMESFET to exclude oxygen.
13. The method of claim 10 comprising the additional step of tuning carrier balance by varying distance between said high barrier surround gate and said first true-ohmic contact metal.
14. The method of claim 10 comprising the additional step of fabricating a first portion of said OMESFET by depositing upon said substrate said semiconductor and said first true-ohmic contact metal and said second true-ohmic contact metal and said high barrier surround gate in pattern and sequence required to produce cooperative elements of said OMESFET.
15. The method of claim 14 comprising the additional step of fabricating a second portion of said OMESFET by printing said source interconnect metal and said gate interconnect metal and said drain interconnect metal upon said first portion of said OMESFET in pattern and in sequence required to produce cooperative elements of said OMESFET.
16. The method of claim 10 comprising the additional steps of:
(a) forming said semiconductor and said first true-ohmic contact metal and said second true-ohmic contact metal and said high barrier surround gate and said source interconnect metal and said gate interconnect metal and said drain interconnect metal into fibers;
(b) organizing said fibers in a warp and a woof of a weaving loom; and
(c) weaving said fibers with said loom thereby forming a weave to fabricate said OMESFET.
17. The method of claim 16 comprising the additional step of affixing said weave to said substrate.