Batch processing of interrupts

1. A computer-implemented method in a processor for handling pending interrupt vectors of a pending interrupt list, comprising:

batch-reading, using said processor, said pending interrupt vectors into a working list of working list interrupt vectors; and

performing, using said processor, interrupt handling of said working list interrupt vectors using an interrupt handling arrangement until said working list is empty, said performing interrupt handling permitting a first incoming interrupt vector that is received by said pending interrupt list after said batch reading to temporarily interrupt said performing interrupt handling of said working list interrupt vectors and to be handled by said processor on a priority basis by said interrupt handling arrangement if a priority level of said first incoming interrupt vector is higher than a priority level of a first working list interrupt vector being currently handled by said interrupt handling arrangement.

2. The computer-implemented method of claim 1 wherein said performing interrupt handling is performed in accordance with a descending order starting with a working list interrupt vector having a highest priority vector number.

3. The computer-implemented method of claim 2 wherein a second incoming interrupt vector that is received by said pending interrupt list after said batch reading is kept in said pending list without being read into said working list for handling by said interrupt handling arrangement if a priority level of said second incoming interrupt vector is equal to said priority level of said first working list interrupt vector being currently handled by said interrupt handling arrangement.

4. The computer-implemented method of claim 2 wherein a second incoming interrupt vector that is received by said pending interrupt list after said batch reading is kept in said pending list without being read into said working list for handling by said interrupt handling arrangement if a priority level of said second incoming interrupt vector is lower than said priority level of said first working list interrupt vector being currently handled by said interrupt handling arrangement.

5. The computer-implemented method of claim 2 further comprising reading a first current priority level value from a first memory location and storing said first current priority level value in a second memory location prior to said batch-reading, said first current priority level tracking a priority level of an interrupt vector handled by said interrupt handling arrangement prior to said batch-reading.

6. The computer-implemented method of claim 5 further comprising restoring said first current priority level value to said first memory location after said working list is exhausted.

7. The computer-implemented method of claim 6 wherein said first memory location represents a task priority register (TPR) of a processor associated with the Itanium® architecture, said pending list represents an IVR control register of said processor.

8. A computer-implemented method in a processor for handling pending interrupt vectors of a pending interrupt list, comprising:

batch-reading, using said processor, all currently pending interrupt vectors into a working list of working list interrupt vectors; and

performing, using said processor, interrupt handling of said working list interrupt vectors using an interrupt handling arrangement until said working list is empty, including

handling said working list interrupt vectors in descending order staring with a working list interrupt vector having a highest priority vector number,

if a first incoming interrupt vector having a priority level that is higher than a priority level associated with a priority level of a first working list interrupt vector being currently handled by said interrupt handling arrangement is received in said pending interrupt list after said batch-reading, temporarily suspending said handling said working list interrupt vectors to handle, using said processor, said first incoming interrupt vector on a priority basis, and

resuming said handling said working list interrupt vectors after said first

incoming interrupt vector is handled.

9. The computer-implemented method of claim 8 further comprising performing another batch-reading, after said working list is exhausted, of pending interrupt vectors that are held in said pending list while said working list is handled.

10. The computer-implemented method of claim 8 further comprising:

if a second incoming interrupt vector having a priority level that is equal to a priority level associated with a priority level of a first working list interrupt vector being currently handled by said interrupt handling arrangement is received in said pending interrupt list after said batch-reading, keeping said second incoming interrupt vector from being handled by said interrupt handling arrangement at least until all working list interrupt vectors having said priority level of said first working list interrupt vector are handled.

11. The computer-implemented method of claim 8 further comprising reading a first current priority level value from a first memory location and storing said first current priority level value in a second memory location prior to said batch-reading, said first current priority level tracking a priority level of an interrupt vector handled by said interrupt handling arrangement prior to said batch-reading.

12. The computer-implemented method of claim 11 further comprising restoring said first current priority level value to said first memory location after said working list is empty.