Thin film transistor array substrate and manufacturing method thereof
View Patent ↗A thin film transistor array substrate, and its manufacturing method, that is made using a three-round mask process. Gate patterns, each of which includes a gate line consisting of a transparent metal pattern and a gate metal pattern, a gate electrode, a lower gate pad, a lower data pad, and a pixel electrode are formed using a first mask process. A second mask process forms a gate insulating pattern and a semiconductor pattern. A third mask process forms source and drain patterns, each of which includes a data line, a source electrode, a drain, electrode, an upper gate pad and an upper data pad. Additionally, the gate metal pattern on an upper portion of the pixel electrode is removed.
1. A method of manufacturing a thin film transistor array substrate of a liquid crystal display, comprising the steps of:
forming a first set of structures on a substrate using a first mask process, wherein the first set of structures includes a gate line, a gate electrode, a gate pad, a data pad, and a pixel electrode, wherein the first set of structures are comprised of a lower transparent conductive pattern and an upper metal pattern;
forming a gate insulating layer, semiconductive layer, and ohmic contract layer over the first set of structures and over the substrate;
forming a photo-resist pattern over the ohmic contact layer that is over the gate line and over the ohmic contact layer that is over the gate electrode;
forming a second set of structures using a second mask process, wherein the second set of structures includes both a gate insulating pattern and a semiconductor pattern over the gate electrode, and a gate insulating pattern and a semiconductor pattern over the gate line, and wherein the second mask process exposes the pixel electrode, the data pad, and the gate pad;
depositing a metal layer over the substrate, over the pixel electrode, over the data pad, over the gate pad, and over the second set of structures; and
etching the deposited metal layer using a third mask process to form spaced apart source and drain electrodes, a gate pad contact hole, a data pad contact hole, data lines, and a storage electrode;
wherein the drain electrode electrically contacts the pixel electrode, wherein the storage electrode electrically contacts the pixel electrode, and wherein the storage electrode is over at least part of the gate line.
2. The method as claimed in claim 1 , wherein forming the photo-resist pattern includes forming a first thickness of photo-resist on a first area, and a second thickness of photo-resist on a second area, wherein the second thickness is less than the first thickness.
3. The method as claimed in claim 2 , wherein forming the photo-resist pattern includes using a diffractive exposure mask.
4. The method as claimed in claim 2 , wherein forming the photo-resist pattern in the second area includes using a semi-transparent mask.
5. The method as claimed in claim 2 , wherein forming the photo-resist pattern includes the step of removing the photo-resist pattern from the second area.
6. The method as claimed in claim 5 , wherein photo-resist is removed from the second area using an ashing process.
7. The method as claimed in claim 1 , wherein etching the deposited metal layer removes the deposited metal layer from the pixel electrode.
8. The method as claimed in claim 1 , wherein the step of forming said semiconductor pattern includes removing a semiconductor material from part of the gate line.
9. The method as claimed in claim 8 , wherein the step of removing a semiconductor material from part of the gate line includes removing the semiconductor material from between subsequently formed data lines.
10. The method as claimed in claim 8 , wherein the step of removing a semiconductor material from part of the gate line includes removing the semiconductor material from an area where a storage electrode is to be formed.