Semiconductor integrated circuit device
View Patent ↗Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.
1. A method of manufacturing a semiconductor integrated circuit device, comprising steps of:
forming trenches in a semiconductor substrate such that said trenches defines active regions and dummy regions not functioning as a semiconductor element;
forming a first insulating film over said trenches;
filling said first insulating film in said trenches by polishing said first insulating film to form element isolation insulating films filled in said trenches;
forming semiconductor elements on said active regions;
forming a second insulating film over said semiconductor elements; and
polishing said second insulating film,
forming dummy interconnections over said second insulating film such that said dummy interconnections do not function as an element;
forming a third insulating film over said dummy interconnections; and
polishing said third insulating film,
wherein said dummy regions and said dummy interconnections are regularly arranged at a scribing area, respectively.
2. A method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein said dummy interconnection is formed by the same level layer as interconnections functioning as bit lines of a dynamic random access memory.
3. A method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein said dummy interconnections are formed over said dummy regions.