IP Library › Granted Patent US 7,030,449
Granted Patent B2
US 7,030,449 · App. 10/951,940 · Granted Apr 18, 2006

Semiconductor integrated circuit device having capacitor element

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Quick Facts
Patent No.
US 7,030,449
App. No.
10/951,940
Granted
Apr 18, 2006
Kind
B2
Abstract

In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

Claims (94)

1. A semiconductor integrated circuit device, comprising:

a semiconductor substrate including a memory cell formed on a memory cell forming region of said substrate;

said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed on said memory cell forming region and a source region and a drain region formed in said substrate,

said first n-channel MISFET being arranged in a first direction adjacent to said first p-channel MISFET such that said gate electrode of said first n-channel MISFET is integrally formed with said gate electrode of said first p-channel MISFET by a first common gate electrode extending in said first direction, and

said second n-channel MISFET being arranged in said first direction adjacent to said second p-channel MISFET such that said gate electrode of said second n-channel MISFET is integrally formed with said gate electrode of said second p-channel MISFET by a second common gate electrode extending in said first direction;

a nitride film containing silicon and nitrogen and formed so as to cover said first common gate electrode and said second common gate electrode and said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFETs;

a first insulating film formed on said nitride film to cover said nitride film such that after planarizing a surface of said first insulating film, said first insulating film is etched by using said nitride film as an etching stopper to form a first opening and a second opening and such that said nitride film within said openings is etched so as to expose said drain region of said second n-channel MISFET in said first opening and to expose said second common gate electrode and said drain region of said first p-channel MISFET in said second opening;

a first conductive film filled in said first opening so as to electrically connect to said drain region of said second n-channel MISFET; and

a second conductive film filled in said second opening so as to electrically connect said second common gate electrode and said drain region of said first p-channel MISFET,

wherein said first common gate electrode, said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET and said first conductive film are electrically connected with each other, and

wherein said second common gate electrode, said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET and said second conductive film are electrically connected with each other.

2. A semiconductor integrated circuit device, comprising:

a semiconductor substrate including a memory cell formed on a memory cell forming region of said substrate,

said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed on said memory cell forming region and a source region and a drain region formed in said substrate,

said first n-channel MISFET being arranged in a first direction adjacent to said first p-channel MISFET such that said gate electrode of said first n-channel MISFET is integrally formed with said gate electrode of said first p-channel MISFET by a first common gate electrode extending in said first direction, and

said second n-channel MISFET being arranged in said first direction adjacent to said second p-channel MISFET such that said gate electrode of said second n-channel MISFET is integrally formed with said gate electrode of said second p-channel MISFET by a second common gate electrode extending in said first direction;

a nitride film containing silicon and nitrogen and formed so as to cover said first common gate electrode and said second common gate electrode and said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFETs;

a first insulating film formed on said nitride film so as to cover said nitride film such that after planarizing a surface of said first insulating film, said first insulating film is etched by using said nitride film as an etching stopper to form a first opening and a second opening and such that said nitride film within said openings is etched to expose said drain region of said second n-channel MISFET in said first opening and to expose said second common gate electrode and said drain region of said first p-channel MISFET in said second opening;

a first conductive film filled in said first opening to electrically connect to said drain region of said second n-channel MISFET;

a second conductive film filled in said second opening to electrically connect said second common gate electrode and said drain region of said first p-channel MISFET,

wherein said first common gate electrode, said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET and said first conductive film are electrically connected with each other, and

wherein said second common gate electrode, said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET and said second conductive film are electrically connected with each other; and

a first power source line and a second power source line formed over said first insulating film of a same level conductive layer,

wherein said first power source line and said second power source line extend in a second direction perpendicular to said first direction.

3. A semiconductor integrated circuit device, comprising:

a semiconductor substrate including a memory cell formed on a memory cell forming region of said substrate,

said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed on said memory cell forming region and a source region and a drain region formed in said substrate,

said first n-channel MISFET being arranged in a first direction adjacent to said first p-channel MISFET such that said gate electrode of said first n-channel MISFET is integrally formed with said gate electrode of said first p-channel MISFET by a first common gate electrode extending in said first direction, and

said second n-channel MISFET being arranged in said first direction adjacent to said second p-channel MISFET such that said gate electrode of said second n-channel MISFET is integrally formed with said gate electrode of said second p-channel MISFET by a second common gate electrode extending in said first direction;

a nitride film containing silicon and nitrogen and formed so as to cover said first common gate electrode and said second common gate electrode and said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFETs;

a first insulating film formed on said nitride film to cover said nitride film such that after planarizing a surface of said first insulating film, said first insulating film is etched by using said nitride film as an etching stopper to form a first opening and a second opening and such that said nitride film within said openings is etched to expose said first common gate electrode and said drain region of said second n-channel MISFET in said first opening and to expose said drain region of said first p-channel MISFET in said second opening;

a first conductive film filled in said first opening to electrically connect to said first common gate electrode and said drain region of said second n-channel MISFET; and

a second conductive film filled in said second opening to electrically connect said drain region of said first p-channel MISFET,

wherein said first common gate electrode, said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET and said first conductive film are electrically connected with each other, and

wherein said second common gate electrode, said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET and said second conductive film are electrically connected with each other.

4. A semiconductor integrated circuit device, comprising:

a semiconductor substrate including a memory cell formed on a memory cell forming region of said substrate,

said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed on said memory cell forming region and a source region and a drain region formed in said substrate,

said first n-channel MISFET being arranged in a first direction adjacent to said first p-channel MISFET such that said gate electrode of said first n-channel MISFET is integrally formed with said gate electrode of said first p-channel MISFET by a first common gate electrode extending in said first direction, and

said second n-channel MISFET being arranged in said first direction adjacent to said second p-channel MISFET such that said gate electrode of said second n-channel MISFET is integrally formed with said gate electrode of said second p-channel MISFET by a second common gate electrode extending in said first direction;

a nitride film containing silicon and nitrogen and formed so as to cover said first common gate electrode and said second common gate electrode and said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFETs;

a first insulating film formed on said nitride film to cover said nitride film such that after planarizing a surface of said first insulating film, said first insulating film is etched by using said nitride film as an etching stopper to form a first opening and a second opening and such that said nitride film within said openings is etched to expose said first common gate electrode and said drain region of said second n-channel MISFET in said first opening and to expose said drain region of said first p-channel MISFET in said second opening;

a first conductive film filled in said first opening to electrically connect to said first common gate electrode and said drain region of said second n-channel MISFET;

a second conductive film filled in said second opening to electrically connect said drain region of said first p-channel MISFET,

wherein said first common gate electrode, said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET and said first conductive film are electrically connected with each other, and

wherein said second common gate electrode, said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET and said second conductive film are electrically connected with each other; and

a first power source line and a second power source line formed over said first insulating film of a same level conductive layer,

wherein said first power source line and said second power source line extend in a second direction perpendicular to said first direction.

5. A semiconductor integrated circuit device, comprising:

a semiconductor substrate including a memory cell formed on a memory cell forming region of said substrate and a peripheral MISFET formed on a peripheral MISFET forming region,

said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed on said memory cell forming region and a source region and a drain region formed in said substrate,

said first n-channel MISFET being arranged in a first direction adjacent to said first p-channel MISFET such that said gate electrode of said first n-channel MISFET is integrally formed with said gate electrode of said first p-channel MISFET by a first common gate electrode extending in said first direction,

said second n-channel MISFET being arranged in said first direction adjacent to said second p-channel MISFET such that said gate electrode of said second n-channel MISFET is integrally formed with said gate electrode of said second p-channel MISFET by a second common gate electrode extending in said first direction, and

said peripheral MISFET including a gate electrode formed on said peripheral MISFET forming region and a source region and a drain region formed in said substrate;

a nitride film containing silicon and nitrogen and formed so as to cover said first common gate electrode and said second common gate electrode, said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFETs, said gate electrode of said peripheral MISFET and said source and drain regions of said peripheral MISFET;

a first insulating film formed on said nitride film to cover said nitride film such that after planarizing a surface of said first insulating film, said first insulating film is etched by using said nitride film as an etching stopper to form a first opening, a second opening and a third opening and such that said nitride film within said openings is etched to expose said drain region of said second n-channel MISFET in said first opening, to expose said second common gate electrode and said drain region of said first p-channel MISFET in said second opening, and to expose said drain region or said source region of said peripheral MISFET in said third opening;

a first conductive film filled in said first opening to electrically connect to said drain region of said second n-channel MISFET;

a second conductive film filled in said second opening to electrically connect said second common gate electrode to said drain region of said first p-channel MISFET; and

a third conductive film filled in said third opening to electrically connect to said drain region or said source region of said peripheral MISFET,

wherein said first common gate electrode, said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET and said first conductive film are electrically connected with each other, and

wherein said second common gate electrode, said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET and said second conductive film are electrically connected with each other.

6. A semiconductor integrated circuit device, comprising:

a semiconductor substrate including a memory cell formed on a memory cell forming region of said substrate and a further MISFET formed on a peripheral circuit forming region,

said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed on said memory cell forming region and a source region and a drain region formed in said substrate,

said gate electrode of said first n-channel MISFET being integrally formed with said gate electrode of said first p-channel MISFET by a first common gate electrode,

said gate electrode of said second n-channel MISFET being integrally formed with said gate electrode of said second p-channel MISFET by a second common gate electrode, and

said further MISFET including a gate electrode formed on said peripheral circuit forming region and a source region and a drain region formed in said substrate;

a nitride film containing silicon and nitrogen and formed so as to cover said first common gate electrode and said second common gate electrode, said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFETs, said gate electrode of said further MISFET and said source region and said drain region of said further MISFET;

a first insulating film formed on said nitride film to cover said nitride film such that after planarizing a surface of said first insulating film, said first insulating film is etched by using said nitride film as an etching stopper to form a first opening, a second opening and a third opening and such that said nitride film within said openings is etched to expose said drain region of said second n-channel MISFET in said first opening, to expose said second common gate electrode and said drain region of said first p-channel MISFET in said second opening, and to expose said drain region or said source region of said further MISFET in said third opening;

a first conductive film filled in said first opening to electrically connect to said drain region of said second n-channel MISFET;

a second conductive film filled in said second opening to electrically connect said second common gate electrode to said drain region of said first p-channel MISFET; and

a third conductive film filled in said third opening to electrically connect to said drain region or said source region of said further MISFET,

wherein said first common gate electrode, said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET and said first conductive film are electrically connected with each other, and

wherein said second common gate electrode, said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET and said second conductive film are electrically connected with each other.

7. A semiconductor integrated circuit device, comprising:

a semiconductor substrate including a memory cell formed on a memory cell forming region of said substrate and a peripheral MISFET formed on a peripheral MISFET forming region,

said memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET and a second p-channel MISFET, each having a gate electrode formed on said memory cell forming region and a source region and a drain region formed in said substrate,

said gate electrode of said first n-channel MISFET being integrally formed with said gate electrode of said first p-channel MISFET by a first common gate electrode,

said gate electrode of said second n-channel MISFET being integrally formed with said gate electrode of said second p-channel MISFET by a second common gate electrode, and

said peripheral MISFET including a gate electrode formed on said peripheral MISFET forming region and a source region and a drain region formed in said substrate;

a silicon nitride film formed to cover said first common gate electrode and said second common gate electrode, said drain regions of said first and second n-channel MISFETs and said first and second p-channel MISFETs, said gate electrode of said peripheral MISFET and said source region and said drain region of said peripheral MISFET;

a first insulating film formed on said nitride film to cover said nitride film such that after planarizing a surface of said first insulating film, said first insulating film is etched by using said silicon nitride film as an etching stopper to form a first opening, a second opening and a third opening and such that said nitride film within said openings is etched to expose said drain region of said second n-channel MISFET in said first opening, to expose said second common gate electrode and said drain region of said first p-channel MISFET in said second opening, and to expose said drain region or said source region of said peripheral MISFET in said third opening;

a first conductive film filled in said first opening to electrically connect to said drain region of said second n-channel MISFET;

a second conductive film filled in said second opening to electrically connect said second common gate electrode to said drain region of said first p-channel MISFET; and

a third conductive film filled in said third opening to electrically connect to said drain region or said source region of said peripheral MISFET,

wherein said first common gate electrode, said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET and said first conductive film are electrically connected with each other, and

wherein said second common gate electrode, said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET and said second conductive film are electrically connected with each other.

8. A semiconductor integrated circuit device according to claim 1 , wherein said nitride film is a silicon nitride film.

9. A semiconductor integrated circuit device according to claim 2 , wherein said nitride film is a silicon nitride film.

10. A semiconductor integrated circuit device according to claim 3 , wherein said nitride film is a silicon nitride film.

11. A semiconductor integrated circuit device according to claim 4 , wherein said nitride film is a silicon nitride film.

12. A semiconductor integrated circuit device according to claim 5 , wherein said nitride film is a silicon nitride film.

13. A semiconductor integrated circuit device according to claim 6 , wherein said nitride film is a silicon nitride film.

14. A semiconductor integrated circuit device according to claim 7 , wherein said nitride film is a silicon nitride film.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 057454/0045 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 052853 FRAME 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Mar 2, 2021
From: ACACIA RESEARCH GROUP LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056775/0066 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2016
From: RENESAS ELECTRONICS CORPORATION
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 038425/0710 →
MERGER Recorded Jul 30, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025204/0512 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2007
From: HITACHI, LTD.
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 019353/0691 →