Deadlock detection and recovery logic for flow control based data path design
View Patent ↗Certain embodiments of the invention may be found in a method and system for handling deadlock conditions in a data processing system. Aspects of the method may comprise identifying a potential deadlock state in a distribute and merge data processing system. An actual deadlock state may be detected once the potential deadlock state is identified. The detected actual deadlock state may be indicated by generating a signal. The method may comprise initiating recovery from deadlock conditions by generating at least one signal that indicates when data is accepted in response to the indication of the actual deadlock state.
1. A method for handling deadlock conditions in a data processing system, the method comprising:
identifying a potential deadlock state when at least one data path is full and at least one other data path is empty;
detecting an actual deadlock state based on said identified potential deadlock state;
generating at least a first signal to indicate said detected actual deadlock state; and
initiating recovery from said detected actual deadlock state by generating at least one signal that enables distribution of data between said at least one data path and said at least one other data path.
2. The method according to claim 1 , comprising receiving at least a first input signal and a first output signal associated with at least a first data path and a second output signal associated with at least a second data path to identify said potential deadlock state.
3. The method according to claim 2 , comprising processing said first input signal and said first output signal associated with said first data path and said second output signal associated with said second data path to identify said potential deadlock state.
4. The method according to claim 3 , comprising generating at least a second signal indicating said identified potential deadlock state.
5. The method according to claim 4 , comprising receiving at least a second input signal and said second output signal associated with said second data path and said first output signal associated with said first data path to identify said potential deadlock state.
6. The method according to claim 5 , comprising processing said second input signal and said second output signal associated with said second data path and said first output signal associated with said first data path to identify said potential deadlock state.
7. The method according to claim 6 , comprising generating at least a third signal indicating said identified potential deadlock state.
8. The method according to claim 7 , comprising generating at least a fourth signal that initializes a counter in response to receiving said generated second signal and said generated third signal detecting said potential deadlock state.
9. The method according to claim 8 , comprising comparing an output of said counter with a particular value to detect said actual deadlock state.
10. The method according to claim 9 , comprising generating said first signal when said output of said counter is greater than said particular value.
11. The method according to claim 10 , comprising receiving said generated first signal detecting said actual deadlock state for said initiating of said recovery.
12. The method according to claim 10 , comprising generating at least a fifth signal associated with said first data path that enables distribution of said data between said first data path and said second data path in response to receiving said generated first signal.
13. The method according to claim 12 , comprising generating at least a sixth signal associated with said second data path that enables distribution of said data between said first data path and said second data path in response to receiving said generated first signal.
14. The method according to claim 1 , comprising identifying said potential deadlock state when at least a first data path is full and at least a second data path is empty.
15. The method according to claim 1 , comprising identifying said potential deadlock state when at least a first data path is empty and at least a second data path is full.
16. A machine-readable storage having stored thereon, a computer program having at least one code section for handling deadlock conditions in a data processing system, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
identifying a potential deadlock state when at least one data path is full and at least one other data path is empty;
detecting an actual deadlock state based on said identified potential deadlock state;
generating at least a first signal to indicate said detected actual deadlock state; and
initiating recovery from said detected actual deadlock state by generating at least one signal that enables distribution of data between said at least one data path and said at least one other data path.
17. The machine-readable storage according to claim 16 , comprising code for receiving at least a first input signal and a first output signal associated with at least a first data path and a second output signal associated with at least a second data path to identify said potential deadlock state.
18. The machine-readable storage according to claim 17 , comprising code for processing said first input signal and said first output signal associated with said first data path and said second output signal associated with said second data path to identify said potential deadlock state.
19. The machine-readable storage according to claim 18 , comprising code for processing said first input signal and said first output signal associated with said first data path and said second output signal associated with said second data path to identify said potential deadlock state.
20. The machine-readable storage according to claim 19 , comprising code for receiving at least a second input signal and said second output signal associated with said second data path and said first output signal associated with said first data path to identify said potential deadlock state.
21. The machine-readable storage according to claim 20 , comprising code for processing said second input signal and said second output signal associated with said second data path and said first output signal associated with said first data path to identify said potential deadlock state.
22. The machine-readable storage according to claim 21 , comprising code for generating at least a third signal indicating said identified potential deadlock state.
23. The machine-readable storage according to claim 22 , comprising code for generating at least a fourth signal that initializes a counter in response to receiving said generated second signal and said generated third signal identifying said potential deadlock state.
24. The machine-readable storage according to claim 23 , comprising code for comparing an output of said counter with a particular value to detect said actual deadlock state.
25. The machine-readable storage according to claim 24 , comprising code for generating said first signal when said output of said counter is greater than said particular value.
26. The machine-readable storage according to claim 25 , comprising code for receiving said generated first signal detecting said actual deadlock state for said initiating of said recovery.
27. The machine-readable storage according to claim 25 , comprising code for generating at least a fifth signal associated with said first data path that enables distribution of said data between said first data path and said second data path in response to receiving said generated first signal.
28. The machine-readable storage according to claim 27 , comprising code for generating at least a sixth signal associated with said second data path that enables distribution of said data between said first data path and said second data path in response to receiving said generated first signal.
29. A system for handling deadlock conditions in a data processing system, the system comprising:
circuitry that enables identification of a potential deadlock state when at least one data path is full and at least one other data path is empty;
circuitry that enables detection of an actual deadlock state based on said identified potential deadlock state;
circuitry that enables generation of at least a first signal that indicates said detected actual deadlock state; and
circuitry that enables initiation of recovery from said detected actual deadlock state by generating at least one signal that enables distribution of data between said at least one data path and said at least one other data path.
30. The system according to claim 29 , comprising circuitry that enables receipt of at least a first input signal and a first output signal associated with at least a first data path and a second output signal associated with at least a second data path to identify said potential deadlock state.
31. A system for handling deadlock conditions in a data processing system, the system comprising:
circuitry that enables identification of a potential deadlock state when at least one data path is full and at least one other data path is empty;
circuitry that enables detection of an actual deadlock state based on said identified potential deadlock state;
circuitry that enables generation of at least a first signal that indicates said detected actual deadlock state; and
circuitry that enables initiation of recovery from said detected actual deadlock state by generating at least one signal that enables distribution of data between said at least one data path and said at least one other data path.
32. The system according to claim 31 , comprising circuitry that enables receipt of at least a first input signal and a first output signal associated with at least a first data path and a second output signal associated with at least a second data path to identify said potential deadlock state.
33. The system according to claim 32 , comprising circuitry that enables processing of said first input signal and said first output signal associated with said first data path and said second output signal associated with said second data path to identify said potential deadlock state.
34. The system according to claim 33 , comprising circuitry that enables generation of at least a second signal indicating said identified potential deadlock state.
35. The system according to claim 34 , comprising circuitry that enables receipt of at least a second input signal and said second output signal associated with said second data path and said first output signal associated with said first data path to identify said potential deadlock state.
36. The system according to claim 35 , comprising circuitry that enables processing of said second input signal and said second output signal associated with said second data path and said first output signal associated with said first data path to identify said potential deadlock state.
37. The system according to claim 36 , comprising circuitry that enables generation of at least a third signal indicating said identified potential deadlock state.
38. The system according to claim 37 , comprising circuitry that enables generation of at least a fourth signal that initializes a counter in response to receiving said generated second signal and said generated third signal identifying said potential deadlock state.
39. The system according to claim 38 , comprising a comparator that compares an output of said counter with a particular value to detect said actual deadlock state.
40. The system according to claim 39 , comprising said comparator that generates said first signal when said output of said counter is greater than said particular value.
41. The system according to claim 40 , comprising circuitry that enables receipt of said generated first signal detecting said actual deadlock state for said initiating of said recovery.
42. The system according to claim 40 , comprising circuitry that enables generation of at least a fifth signal associated with said first data path that enables distribution of said data between said first data path and said second data path in response to receiving said generated first signal.
43. The system according to claim 42 , comprising circuitry that enables generation of at least a sixth signal associated with said second data path that enables distribution of said data between said first data path and said second data path in response to receiving said generated first signal.
44. The system according to claim 31 , comprising circuitry that enables identification of said potential deadlock state when at least a first data path is full and at least a second data path is empty.
45. The system according to claim 31 , comprising circuitry that enables identification of said potential deadlock state when at least a first data path is empty and at least a second data path is full.