IP Library Granted Patent US 7,590,118
Granted Patent B2
US 7,590,118 · App. 10/955,947 · Granted Sep 15, 2009

Frame aggregation format

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Quick Facts
Patent No.
US 7,590,118
App. No.
10/955,947
Granted
Sep 15, 2009
Kind
B2
Abstract

A frame format for frame aggregation into a physical-layer packet employs an aggregated frame descriptor appended to one or more sub-frames. Each sub-frame comprises a header comprising logical-layer and sub-frame protocol information, optional verification information to verify the sub-frame data, and aggregated user data. The aggregated frame descriptor includes information identifying the packet as conforming to an aggregated frame format, and sub-frame descriptors identifying at least one of a position, a length, and a data rate of a corresponding sub-frame. The aggregated frame is then formed into a physical layer packet for transmission through a medium.

Claims (55)

1. A receiving device-implemented method of generating an aggregate frame for a plurality of sub-frames, each sub-frame containing user data, the method comprising the steps of:

(a) the receiving device forming an aggregate data unit (ADU) from two or more sub-frames; and

(b) the receiving device generating an aggregate frame comprising:

(1) an aggregate frame descriptor including (i) an aggregate frame header indicating a type of frame, (ii) a value representing the number of sub-frames of the ADU, and (iii) a sub-frame descriptor including, for each of the two or more sub-frames, an address of a receiving device for the corresponding sub-frame; and

(2) the ADU,

wherein the addresses of receiving devices for the two or more sub-frames in the ADU are positioned, in the aggregate frame, before the ADU comprising the two or more sub-frames.

2. The invention as recited in claim 1 , further comprising the step of the receiving device adding an aggregate error control field to the ADU, the aggregate error control field having error detection/correction information for the aggregate frame.

3. The invention as recited in claim 2 , wherein the added aggregate error control field is a frame checksum.

4. The invention as recited in claim 1 , further comprising the step of the receiving device generating a physical layer packet from the aggregate frame.

5. The invention as recited in claim 4 , further comprising the step of the receiving device transmitting the physical layer packet through a medium.

6. The invention as recited in claim 4 , wherein the step of generating the physical layer packet comprises the step of adding a preamble and a physical layer header.

7. The invention as recited in claim 1 , wherein step (a) further comprises the step of ordering the position of each of the sub-frames in the ADU based on a data rate of the sub-frame.

8. The invention as recited in claim 1 , wherein, for step (a), the position of each of the sub-frames in the ADU is ordered based on differing data rates of the sub-frames.

9. The invention as recited in claim 1 , wherein, for step (a), the position of each of the sub-frames in the ADU is ordered based on increasing data rate.

10. The invention as recited in claim 1 , wherein, for step (a), each sub-frame comprises a sub-frame header and sub-frame data.

11. The invention as recited in claim 10 , wherein, for step (a), each sub-frame further comprises a sub-frame error control field having error detection/correction information for the sub-frame.

12. The invention as recited in claim 1 , wherein, for step (b), the aggregate frame header comprises a frame control field indicating the type of frame is an aggregate frame.

13. The invention as recited in claim 12 , wherein, for step (b), the aggregate frame descriptor further comprises an error control field having error detection/correction information for the aggregate frame descriptor.

14. The invention as recited in claim 1 , wherein, for step (b), each sub-frame descriptor comprises an address corresponding to a receiving device for the associated sub-frame, and position information identifying a position of the associated sub-frame within the aggregate frame.

15. The invention as recited in claim 14 , wherein, for step (b), each sub-frame descriptor comprises an error control field having error detection/correction information for the corresponding sub-frame.

16. The invention as recited in claim 1 , wherein the receiving device includes a processor of an integrated circuit (IC), the processor adapted to perform the method steps.

17. The invention as recited in claim 16 , wherein the IC is embodied in a device operating in accordance with an IEEE 802.11 standard for wireless local area networks.

18. Apparatus for generating an aggregate frame for a plurality of sub-frames, the apparatus comprising:

a first circuit adapted to form an aggregate data unit (ADU) from two or more sub-frames; and

a second circuit adapted to generate an aggregate frame comprising:

(1) an aggregate frame descriptor including (i) an aggregate frame header indicating a type of frame, (ii) a value representing the number of sub-frames of the ADU, and (iii) a sub-frame descriptor including, for each of the two or more sub-frames, an address of a receiving device for the corresponding sub-frame; and

(2) the ADU,

wherein the addresses of receiving devices for the two or more sub-frames in the ADU are positioned, in the aggregate frame, before the ADU comprising the two or more sub-frames.

19. A method of processing a packet by a receiving device, the method comprising the steps of:

(a) the receiving device receiving a frame type of the packet;

(b) the receiving device receiving, if the frame type is an aggregate frame, one or more descriptors corresponding to two or more sub-frames of the packet, the one or more descriptors including, for each of the two or more sub-frames, an address of a receiving device for the corresponding sub-frame;

(c) the receiving device determining, for each descriptor, whether the corresponding sub-frame is for the receiving device; and

(d) the receiving device extracting, for each sub-frame determined to be for the receiving device, a corresponding data frame,

wherein the addresses of receiving devices for the two or more sub-frames in the packet are positioned, in the aggregate frame, before the packet comprising the two or more sub-frames.

20. The invention as recited in claim 19 , further comprising the step of the receiving device verifying, for each sub-frame determined to be for the receiving device, error detection/correction information corresponding to the sub-frame.

21. The invention as recited in claim 20 , further comprising the step of the receiving device correcting one or more errors based on the error detection/correction information.

22. The invention as recited in claim 19 , wherein step (d) comprises the step of detecting the position and length of the sub-frame in the packet.

23. The invention as recited in claim 19 , wherein the receiving device includes a processor of an integrated circuit (IC), the processor adapted to perform the method steps.

24. The invention as recited in claim 23 , wherein the IC is embodied in a device operating in accordance with an IEEE 802.11 standard for wireless local area networks.

25. A receiving device for processing a packet comprising:

a first circuit adapted to receive, if a frame type of the packet is an aggregate frame, one or more descriptors corresponding to two or more sub-frames of the packet, the one or more descriptors including, for each of the two or more sub-frames, an address of a receiving device for the corresponding sub-frame; and

a second circuit adapted to i) determine, for each descriptor, whether the corresponding sub-frame is for the receiving device and ii) extract, for each sub-frame determined to be for the receiving device, a corresponding data frame,

wherein the addresses of receiving devices for the two or more sub-frames in the packet are positioned, in the aggregate frame, before the packet comprising the two or more sub-frames.

26. A computer-readable storage medium having stored thereon a plurality of instructions, the plurality of instructions including instructions which, when executed by a processor, cause the processor to implement a method for generating an aggregate frame for a plurality of sub-frames, each sub-frame containing user data, the method comprising the steps of:

(a) forming an aggregate data unit (ADU) from two or more sub-frames; and

(b) generating an aggregate frame comprising:

(1) an aggregate frame descriptor including (i) an aggregate frame header indicating a type of frame, (ii) a value representing the number of sub-frames of the ADU, and (iii) a sub-frame descriptor including, for each of the two or more sub-frames, an address of a receiving device for the corresponding sub-frame; and

(2) the ADU,

wherein the addresses of receiving devices for the two or more sub-frames in the ADU are positioned, in the aggregate frame, before the ADU comprising the two or more sub-frames.

27. A computer-readable storage medium having stored thereon a plurality of instructions, the plurality of instructions including instructions which, when executed by a processor, cause the processor to implement a method for generating an aggregate frame for a plurality of sub-frames, the method comprising the steps of:

(a) receiving a frame type of the packet;

(b) receiving, if the frame type is an aggregate frame, one or more descriptors corresponding to two or more sub-frames of the packet, the one or more descriptors including, for each of the two or more sub-frames, an address of a receiving device for the corresponding sub-frame;

(c) determining, for each descriptor, whether the corresponding sub-frame is for the receiving device; and

(d) extracting, for each sub-frame determined to be for the receiving device, a corresponding data frame,

wherein the addresses of receiving devices for the two or more sub-frames in the packet are positioned, in the aggregate frame, before the packet comprising the two or more sub-frames.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
MERGER Recorded Feb 20, 2015
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 035058/0895 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035059/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2004
From: GIESBERTS, PIETER-PAUL S.; VAN LEEUWEN, RICHARD M.
To: AGERE SYSTEMS INC.
Reel/Frame 016044/0187 →