IP Library Granted Patent US 7,554,464
Granted Patent B1
US 7,554,464 · App. 10/956,377 · Granted Jun 30, 2009

Method and system for processing data having a pattern of repeating bits

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Quick Facts
Patent No.
US 7,554,464
App. No.
10/956,377
Granted
Jun 30, 2009
Kind
B1
Abstract

A method and system allows for fast compression and decompressing of data using existing repetitive interleaved patterns within scientific data (floating point, integer, and image). An advantage of the method and system is that it is so fast that it can be used to save time due to a lower amount of data transferred/stored in scenarios like network transfer, disk or memory storage, cache storage or any other real-time applications where time plays a crucial role.

Claims (75)

1. A method of processing data, comprising:

identifying a repeating pattern of bits that occurs a plurality of times within the data;

identifying a given stride of non-contiguous bits at which the identified repeating pattern repeats the plurality of times within the data; and

using the identified repeating pattern and given stride to process the data.

2. A method according to claim 1 , wherein the using step includes:

replacing the repeating pattern of bits with one or more bits of information corresponding to the repeating pattern.

3. A method according to claim 2 , wherein the information comprises fewer bits than the repeating pattern.

4. A method according to claim 1 , further comprising:

completing the step of identifying the repeating pattern of bits in one pass through the data.

5. A method according to claim 2 , further comprising:

completing the step of identifying the repeating pattern of bits in one pass through the data; and

preparing a compressed version of the data.

6. A method according to claim 5 , further comprising:

receiving the compressed version of the data; and

decompressing the compressed version to obtain the data using the information.

7. A method according to claim 1 , further comprising:

identifying another pattern of bits that occurs more than once at another stride of non-contiguous bits within the data.

8. A method according to claim 7 , wherein the another pattern of bits is within the given stride of the repeating pattern of bits.

9. A method according to claim 1 , wherein the data is scientific data.

10. A method according to claim 1 , wherein the data is floating point data.

11. A method according to claim 1 , wherein the data is pixel data.

12. An apparatus for processing data, comprising:

means for identifying a repeating pattern of bits that occurs a plurality of times within the data;

means for identifying a given stride of non-contiguous bits at which the identified repeating pattern repeats the plurality of times within the data; and

means for using the identified repeating pattern and given stride to process the data.

13. An apparatus according to claim 12 , wherein the means for using includes:

means for replacing the repeating pattern of bits with one or more bits of information corresponding to the repeating pattern.

14. An apparatus according to claim 13 , wherein the information comprises fewer bits than the repeating pattern.

15. An apparatus according to claim 12 , wherein the identifying means is operative to complete identifying the repeating pattern of bits in one pass through the data.

16. An apparatus according to claim 13 , further comprising:

means for preparing a compressed version of the data.

17. An apparatus according to claim 16 , further comprising:

means for receiving the compressed version of the data; and

means for decompressing the compressed version to obtain the data using the information.

18. An apparatus according to claim 12 , further comprising:

means for identifying another pattern of bits that occurs more than once at another stride of non-contiguous bits within the data.

19. An apparatus according to claim 18 , wherein the another pattern of bits is within the given stride of the repeating pattern of bits.

20. A system comprising:

a first processor that communicates data with a second processor over a channel, the first processor comprising:

a compressor that identifies a pattern of bits that occurs more than once at a given stride of non-contiguous bits within the data, and prepares a compressed version of the data for sending over the channel, the compressed version of the data including information about the pattern.

21. A system according to claim 20 , wherein the second processor comprises:

a decompressor that is operative to retrieve the data from the compressed version of the data using the information.

22. A system according to claim 20 , wherein the information comprises fewer bits than the identified pattern.

23. A method of processing data, comprising:

identifying a repeating pattern of bits that occurs more than once at a given stride of non-contiguous bits within the data; and

replacing the repeating pattern of bits with one or more bits of information corresponding to the repeating pattern,

wherein the bits of information comprises fewer bits than the repeating pattern.

24. A method of processing data, comprising:

identifying a repeating pattern of bits that occurs more than once at a given stride of non-contiguous bits within the data;

replacing the repeating pattern of bits with one or more bits of information corresponding to the repeating pattern;

completing the step of identifying the repeating pattern of bits in one pass through the data; and

preparing a compressed version of the data.

25. A method according to claim 24 , further comprising:

receiving the compressed version of the data; and

decompressing the compressed version to obtain the data using the information.

26. An apparatus processing data, comprising:

means for identifying a repeating pattern of bits that occurs more than once at a given stride of non-contiguous bits within the data; and

means for replacing the repeating pattern of bits with one or more bits of information corresponding to the repeating pattern,

wherein the information comprises fewer bits than the repeating pattern.

27. An apparatus for processing data, comprising:

means for identifying a repeating pattern of bits that occurs more than once at a given stride of non-contiguous bits within the data;

means for replacing the repeating pattern of bits with one or more bits of information corresponding to the repeating pattern; and

means for preparing a compressed version of the data.

28. An apparatus according to claim 27 , further comprising:

means for receiving the compressed version of the data; and

means for decompressing the compressed version to obtain the data using the information.

29. An apparatus for processing data, comprising:

means for identifying a repeating pattern of bits that occurs more than once at a given stride of non-contiguous bits within the data;

means for replacing the repeating pattern of bits with one or more bits of information corresponding to the repeating pattern; and

means for identifying another pattern of bits that occurs more than once at a another stride of non-contiguous bits within the data.

30. A system comprising:

a first processor that communicates data with a second processor over a channel, the first processor comprising:

a compressor that identifies a pattern of bits that occurs more than once at a given stride of non-contiguous bits within the data, and prepares a compressed version of the data for sending over the channel, the compressed version of the data including information about the pattern, and

wherein the second processor comprises:

a decompressor that is operative to retrieve the data from the compressed version of the data using the information.

Assignments (16)
CORRECTIVE ASSIGNMENT TO REMOVE US PATENT NO. 9013874 PREVIOUSLY RECORDED UNDER REEL AND FRAME 064272/0249. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 17, 2024
From: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC)
To: INNOVATIONS IN MEMORY LLC
Reel/Frame 068998/0780 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2023
From: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC)
To: INNOVATIONS IN MEMORY LLC
Reel/Frame 064272/0249 →
RELEASE OF SECURITY INTEREST Recorded Jun 16, 2021
From: SILICON VALLEY BANK
To: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC (F/K/A VIOLIN MEMORY, INC.))
Reel/Frame 056600/0186 →
CHANGE OF NAME Recorded May 25, 2021
From: VIOLIN SYSTEMS LLC
To: VSIP HOLDINGS LLC
Reel/Frame 056366/0849 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2018
From: SILICON VALLEY BANK
To: VIOLIN SYSTEMS LLC
Reel/Frame 044664/0504 →
CHANGE OF NAME Recorded Dec 19, 2017
From: VIOLIN MEMORY, INC.
To: VIOLIN SYSTEMS LLC
Reel/Frame 044908/0680 →
SECURITY INTEREST Recorded Aug 27, 2014
From: VIOLIN MEMORY, INC.
To: SILICON VALLEY BANK
Reel/Frame 033645/0834 →
RELEASE OF SECURITY INTEREST Recorded Aug 26, 2014
From: COMERICA BANK
To: VIOLIN MEMORY, INC.
Reel/Frame 033617/0360 →
RELEASE OF SECURITY INTEREST Recorded Aug 22, 2014
From: TRIPLEPOINT CAPITAL LLC
To: VIOLIN MEMORY, INC.
Reel/Frame 033591/0759 →
RELEASE OF SECURITY INTEREST Recorded Aug 5, 2014
From: TRIPLEPOINT CAPITAL LLC
To: VIOLIN MEMORY INC
Reel/Frame 033473/0377 →
SECURITY AGREEMENT Recorded Jul 19, 2013
From: VIOLIN MEMORY, INC.
To: COMERICA BANK, A TEXAS BANKING ASSOCIATION
Reel/Frame 030833/0440 →
SECURITY AGREEMENT Recorded May 16, 2013
From: VIOLIN MEMORY, INC.
To: TRIPLEPOINT CAPITAL LLC
Reel/Frame 030426/0821 →
CHANGE OF NAME Recorded Aug 10, 2010
From: GEAR SIX, INC.
To: GEAR6(ASSIGNMENT FOR THE BENEFIT OF CREDITORS)LLC
Reel/Frame 024813/0027 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2010
From: GEAR6(ASSIGNMENT FOR THE BENEFIT OF CREDITORS)LLC
To: VIOLIN MEMORY, INC.
Reel/Frame 024814/0008 →
CHANGE OF NAME Recorded Feb 2, 2007
From: ENGINEERED INTELLIGENCE CORPORATION
To: GEAR SIX, INC.
Reel/Frame 018849/0704 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2005
From: OBERDORFER, MATTHIAS
To: ENGINEERED INTELLIGENCE CORPORATION
Reel/Frame 015619/0030 →