Complementary output resistive memory cell
View Patent ↗A complementary resistive memory structure is provided comprising a common source electrode and a first electrode separated from the common source electrode by resistive memory material; and a second electrode adjacent to the first electrode and separated from the common source electrode by resistive memory material, along with accompanying circuitry and methods of programming and reading the complementary resistive memory structure.
1. A memory structure comprising:
a first memory resistor connected between a first voltage source and a first active transistor at a first active transistor source; a first load transistor connected between a drain voltage and the first active transistor at a first active transistor drain; and a first output connected at the first active transistor drain;
a second memory resistor connected between a second voltage source and a second active transistor at a second active transistor source; a second load transistor connected between the drain voltage and the second active transistor at a second active transistor drain; and a second output connected at the second active transistor drain; and
a word line connected to a gate of the first active transistor and to a gate of the second active transistor
wherein, with one of the first memory resistor and second memory resistor set to a high resistance and the other of the first memory resistor and second memory resistor set to a low resistance, the output connected to one of the memory resistors is high and the output connected to the other of the memory resistors is low.
2. The memory structure of claim 1 , wherein the first memory resistor comprises a colossal magnetoresistance (CMR) material.
3. The memory structure of claim 1 , wherein the first memory resistor comprises Pr 1-x Ca x MnO 3 (PCMO).
4. The memory structure of claim 1 , wherein the first memory resistor comprises Gd 1-x Ca x BaCo 2 O 5+5 .
5. A method of programming a complementary resistive memory structure having a common electrode separated from a first electrode in a first active transistor and a second electrode in a second active transistor by a resistive memory material comprising:
grounding the first electrode in the first active transistor;
allowing the common electrode to float; and
applying a programming pulse to the second electrode in the second active transistor.
6. The method of claim 5 , wherein the programming pulse is a positive pulse.
7. The method of claim 5 , wherein the programming pulse is a negative pulse.
8. The method of claim 5 , wherein the programming pulse is applied through the second active transistor connected to the second electrode, wherein the second active transistor has a gate and wherein the programming pulse is applied to the gate of the second active transistor.