Thin film transistor array substrate and method of manufacturing the same
View Patent ↗A thin film transistor array substrate includes a gate pattern on a substrate. The gate pattern includes a gate electrode, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line. A source/drain pattern includes a source electrode and a drain electrode, a data line connected to the source electrode, and a lower data pad electrode connected to the data line. A semiconductor pattern is formed beneath the source/drain pattern. A transparent electrode pattern includes a pixel electrode connected to the drain electrode, an upper gate pad electrode connected to the lower gate pad electrode, and an upper data pad electrode connected to the lower data pad electrode. The thin film array substrate further includes a gate insulating pattern and a passivation film pattern stacked at remaining areas excluding areas within which the transparent electrode pattern is formed.
1. A thin film transistor array substrate, comprising:
a gate pattern on a substrate, the gate pattern including a gate electrode of a thin film transistor, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line;
a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, and a lower data pad electrode connected to the data line;
a semiconductor pattern formed beneath the source/drain pattern;
a transparent electrode pattern including a pixel electrode connected to the drain electrode, an upper gate pad electrode connected to the lower gate pad electrode, and an upper data pad electrode connected to the lower data pad electrode; and
a gate insulating pattern and a passivation film pattern stacked at remaining areas excluding areas within which the transparent electrode pattern is formed, wherein one end of the drain electrode has a flat surface and an inclined slope surface, an entire surface of the flat surface is covered with the passivation film pattern, and an entire surface of the inclined slope surface is covered with the pixel electrode.
2. The thin film transistor array substrate of claim 1 , wherein the source/drain pattern includes at least one of molybdenum (Mo), molybdenum alloy (Mo alloy), and aluminum neodium (AlNd).
3. The thin film transistor array substrate of claim 1 , further comprising a storage capacitor including the gate line and a storage electrode overlapping the gate line, with the gate insulating pattern and the semiconductor pattern positioned therebetween.
4. The thin film transistor array substrate of claim 3 , wherein a lateral surface of the storage electrode is uncovered with respect to the passivation film pattern.
5. The thin film transistor array substrate of claim 1 , wherein the inclined slope of the drain electrode at a lateral surface is formed over a horizontal dimension of about 0.1 μm to 1 μm.