Divider module for use in an oscillation synthesizer
View Patent ↗A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably coupled to produce a divider value based on a control signal. The logic circuit is operably coupled to produce the control signal based on divider select signals. Each of the plurality of flip-flops includes a first differential latch module, a second differential latch module. The first differential latch module is operably coupled to produce a differential latched signal based on a differential flip-flop input signal. The second differential latch module is operably coupled to produce a differential flip-flop output based on the differential latched signal. Each of the first and second differential latch modules includes a sample transistor section, a hold transistor section, a first gating circuit, and a second gating circuit.
1. A divider module for use in an oscillation synthesizer, the divider module comprises:
plurality of flip-flops interoperably coupled to produce a divider value based on a control signal; and
logic circuit operably coupled to produce the control signal based on divider select signals, wherein each of the plurality of flip-flops includes:
first differential latch module operably coupled to produce a differential latched signal based on a differential flip-flop input signal; and
second differential latch module operably coupled to produce a differential flip-flop output based on the differential latched signal, wherein the first and second differential latch modules each includes:
sample transistor section operably coupled to sample, when coupled to a supply voltage, a differential input signal to produce a sampled differential input signal;
hold transistor section operably coupled to latch, when coupled to the supply voltage, the sampled differential input signal thereby producing a latched differential signal;
first gating circuit operable to couple the sample transistor section to the supply voltage in accordance with a first clocking logic operation and a second clocking logic operation, wherein the first clocking logic operation is based on a negative leg and a positive leg of a differential clock signal, and wherein the second clocking logic operation is based on the negative leg and the positive leg of the differential clock signal; and
second gating circuit operable to couple the hold transistor section to the supply voltage in accordance with a third clocking logic operation and a fourth clocking logic operation, wherein the third clocking logic operation is based on the negative leg and the positive leg of the differential clock signal, and wherein the fourth clocking logic operation is based on the negative leg and the positive leg of the differential clock signal.
2. The divider module of claim 1 , wherein the first gating circuit further comprises:
first enable transistor operable to couple the sample transistor section to a first potential of the supply voltage based on the positive leg of the differential clock signal;
second enable transistor operable to couple the sample transistor section to a second potential of the supply voltage based on the negative leg of the differential clock signal;
first clock skew correction module operably coupled in parallel with the first enable transistor, wherein the first clock skew correction module couples the sample transistor section to the first potential based on a first logic function of the positive and negative legs of the differential clock signal; and
second clock skew correction module operably coupled in parallel with the second enable transistor, wherein the second clock skew correction module couples the sample transistor section to the second potential based on a second logic function of the positive and negative legs of the differential clock signal.
3. The divider module of claim 2 , wherein the first clock skew correction module further comprises:
a P-channel transistor having a gate, a drain, and a source, wherein the source is coupled to the first potential, the drain is coupled to the sample transistor section, and the gate is coupled to receive a first clock skew correction signal; and
NAND gate operably coupled to produce the first clock skew correction signal based on the negative and positive legs of the differential clock signal.
4. The divider module of claim 2 , wherein the second clock skew correction module further comprises:
an N-channel transistor having a gate, a drain, and a source, wherein the source is coupled to the second potential, the drain is coupled to the sample transistor section, and the gate is coupled to receive a second clock skew correction signal; and
NOR gate operably coupled to produce the second clock skew correction signal based on the negative and positive legs of the differential clock signal.
5. The divider module of claim 1 , wherein the second gating circuit further comprises:
first enable transistor operable to couple the hold transistor section to a first potential of the supply voltage based on the negative leg of the differential clock signal;
second enable transistor operable to couple the hold transistor section to a second potential of the supply voltage based on the positive leg of the differential clock signal;
first clock skew correction module operably coupled in series with the first enable transistor, wherein the first clock skew correction module couples the hold transistor section to the first potential based on a second logic function of the positive and negative legs of the differential clock signal; and
second clock skew correction module operably coupled in series with the second enable transistor, wherein the second clock skew correction module couples the hold transistor section to the second potential based on a first logic function of the positive and negative legs of the differential clock signal.
6. The divider module of claim 5 , wherein the first clock skew correction module further comprises:
a P-channel transistor having a gate, a drain, and a source, wherein the drain is coupled to the hold transistor section, and the gate is coupled to receive a first clock skew correction signal; and
NOR gate operably coupled to produce the first clock skew correction signal based on the negative and positive legs of the differential clock signal.
7. The divider module of claim 5 , wherein the second clock skew correction module further comprises:
an N-channel transistor having a gate, a drain, and a source, wherein the drain is coupled to the hold transistor section and the gate is coupled to receive a second clock skew correction signal; and
NAND gate operably coupled to produce the second clock skew correction signal based on the negative and positive legs of the differential clock signal.
8. The divider module of claim 1 , wherein the first gating circuit further comprises:
first enable transistor operable to couple the sample transistor section to a first potential of the supply voltage based on the positive leg of the differential clock signal;
second enable transistor operable to couple the sample transistor section to a second potential of the supply voltage based on the negative leg of the differential clock signal;
first clock skew correction module operably coupled in series with the first enable transistor, wherein the first clock skew correction module couples the sample transistor section to the first potential based on a second logic function of the positive and negative legs of the differential clock signal; and
second clock skew correction module operably coupled in series with the second enable transistor, wherein the second clock skew correction module couples the sample transistor section to the second potential based on a first logic function of the positive and negative legs of the differential clock signal.
9. The divider module of claim 8 , wherein the first clock skew correction module further comprises:
a P-channel transistor having a gate, a drain, and a source, wherein the drain is coupled to the hold transistor section, and the gate is coupled to receive a first clock skew correction signal; and
NOR gate operably coupled to produce the first clock skew correction signal based on the negative and positive legs of the differential clock signal.
10. The divider module of claim 8 , wherein the second clock skew correction module further comprises:
an N-channel transistor having a gate, a drain, and a source, wherein the drain is coupled to the hold transistor section and the gate is coupled to receive a second clock skew correction signal; and
NAND gate operably coupled to produce the second clock skew correction signal based on the negative and positive legs of the differential clock signal.
11. The divider module of claim 1 , wherein the second gating circuit further comprises:
first enable transistor operable to couple the hold transistor section to a first potential of the supply voltage based on the negative leg of the differential clock signal;
second enable transistor operable to couple the hold transistor section to a second potential of the supply voltage based on the positive leg of the differential clock signal;
first clock skew correction module operably coupled in parallel with the first enable transistor, wherein the first clock skew correction module couples the hold transistor section to the first potential based on a first logic function of the positive and negative legs of the differential clock signal; and
second clock skew correction module operably coupled in parallel with the second enable transistor, wherein the second clock skew correction module couples the hold transistor section to the second potential based on a second logic function of the positive and negative legs of the differential clock signal.
12. The divider module of claim 11 , wherein the first clock skew correction module further comprises:
a P-channel transistor having a gate, a drain, and a source, wherein the source is coupled to the first potential, the drain is coupled to the hold transistor section, and the gate is coupled to receive a first clock skew correction signal; and
NAND gate operably coupled to produce the first clock skew correction signal based on the negative and positive legs of the differential clock signal.
13. The divider module of claim 11 , wherein the second clock skew correction module further comprises:
an N-channel transistor having a gate, a drain, and a source, wherein the source is coupled to the second potential, the drain is coupled to the hold transistor section, and the gate is coupled to receive a second clock skew correction signal; and
NOR gate operably coupled to produce the second clock skew correction signal based on the negative and positive legs of the differential clock signal.