Apparatus and method for delay matching of full and divided clock signals
View Patent ↗A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.
1. A system, comprising:
a clock generator that generates first and second clock signals;
a clock buffer that produces clock output signals at first and second clock signal output terminals based on the first and second clock signals;
a clock divider that divides the first and second clock signals into first and second divided clock signals, the second divided clock signal having a frequency that is a harmonic of a frequency of the first divided clock signal; and
a transmission delay matching device that produces first and second divided clock output signals at first and second divided clock signal output terminals based on the first and second clock signals received at first and second input terminals, such that there is a reduction in time in a transition of the amplitude of the first and second divided clock output signals to a steady state value.
2. The system of claim 1 , wherein said transition delay matching device comprises:
a clock buffer section that produces the first and second divided clock output signals; and
an amplitude adjusting section that limits the amplitude of the first and second divided output signals.
3. The system of claim 2 , wherein said amplitude adjusting section limits a divided clock steady state voltage differential between the amplitudes of the first and second divided clock output signals.
4. The system of claim 2 , wherein said amplitude adjusting section includes a resistor coupled between the first and second output terminals.
5. The system of claim 2 , wherein said amplitude adjusting section comprises:
a first resistor coupled between the a first output terminal and a common node, wherein a voltage source is coupled to the common node; and
a second resistor coupled between the second terminal and the common node.
6. The system of claim 2 , wherein said clock buffer section comprises:
a first clock buffer device coupled to the first input terminal that produces the first divided clock output signal; and
a second clock buffer device coupled to the second input terminal that produces the second divided clock output signal,
wherein said amplitude adjusting section limits a divided clock steady state voltage differential between the first and second divided clock output signals.
7. The system of claim 6 , wherein said amplitude adjusting section comprises:
a first resistor coupled between an output terminal of the first output buffer device and a first voltage source; and
a second resistor coupled between an output terminal of the second output buffer device and a second voltage source.
8. The system of claim 1 , wherein the first clock signal is in phase with the first divided clock signals and the second clock signal is in phase with the second divided clock signals.
9. A method, comprising:
generating first and second clock signals;
producing clock output signals at first and second clock signal output terminals based on the first and second clock signals;
dividing the first and second clock signals into first and second divided clock signals having first and second frequencies, respectively, such that the second frequency is a harmonic of the first frequency; and
producing first and second divided clock output signals at first and second divided clock signal output terminals based on the first and second clock signals received at first and second input terminals, such that there is a reduction in time in a transition of the amplitude of the first and second divided clock output signals to a steady state value.
10. The method of claim 9 , further comprising:
limiting the amplitude of at least one of the first and second divided output signals.
11. The method of claim 9 , further comprising:
limiting a divided clock steady state voltage differential between the amplitudes of the first and second divided clock output signals.