Image sticking elimination circuit

1. An image sticking elimination circuit for an abnormal power-off of a display unit, said image sticking elimination circuit being coupled to a gate drive circuit and a voltage converter, said image sticking elimination circuit comprising:

a charge storage device having a first terminal and a second terminal, said first terminal of said charge storage device being coupled to a first voltage terminal of said voltage converter, said second terminal of said charge storage device being coupled to a ground; and

a diode having a first terminal and a second terminal, said first terminal of said diode being coupled to said first voltage terminal of said voltage converter, said second terminal of said diode being coupled to said first terminal of said charge storage device;

an isolation device having a first terminal, a second terminal, and a third terminal, said first terminal of said isolation device being coupled to said first terminal of said charge storage device, said second terminal of said isolation device being coupled to and between said first voltage terminal of said voltage converter and said first terminal of said diode, said third terminal of said isolation device being coupled to a second voltage terminal of said gate drive circuit, said isolation device being turned on when said abnormal power-off of a display occurs;

wherein said charge storage device releases charges stored therein when said isolation device is turned on.

2. The circuit of claim 1 , wherein a current flows from said first terminal of said diode to said second terminal of said diode, wherein said isolation device is a P-type field effect transistor.

3. The circuit of claim 2 , wherein a terminal of said gate drive circuit is coupled to said first voltage terminal of said voltage converter, and an another terminal of said gate drive circuit is coupled to said second voltage terminal of said voltage converter.

4. The circuit of claim 1 , wherein a current flows from said second terminal of said diode to said first terminal of said diode, wherein said isolation device is a N-type field effect transistor.

5. The circuit of claim 1 , wherein said charge storage device is a capacitor.

6. The circuit of claim 1 , wherein said voltage converter is a DC-to-DC converter.

7. The circuit of claim 1 , wherein said display unit is a liquid crystal display unit.

8. The circuit of claim 1 , wherein said display unit is an organic light emitting diode unit.

9. The circuit of claim 1 , wherein said first voltage terminal is a high voltage terminal and said second voltage terminal is a low voltage terminal.

10. A display device, comprising:

a pixel unit;

a data driver, coupled to the pixel unit; and

a gate driver as in claim 1 , coupled to the pixel unit.

11. An electronic device, comprising:

a display device as in claim 10 ;

a source of data image;

a controller operatively coupled to the display device and the source, providing the image data to render an image on the display.

12. An image sticking elimination circuit, said image sticking elimination circuit being coupled to a voltage converter and a gate drive circuit, comprising:

a first terminal, directly coupled to a first voltage terminal of said voltage converter, wherein a second voltage terminal of said voltage converter is coupled directly to a first voltage terminal of said gate drive circuit;

a second terminal, coupled to a second voltage terminal of said gate drive circuit; and

a resistor, coupled to and between said first terminal and said second terminal,

wherein the voltage converter comprises a parasitic capacitance having one terminal coupled to the first terminal, and another terminal coupled to the second terminal and the second voltage terminal of the gate drive circuit via a resistor and capacitor circuit, and wherein said one and another terminals of the parasitic capacitance are directly coupled to the first voltage terminal and second voltage terminal, respectively, of the voltage converter.

13. The circuit of claim 12 , further comprising a diode having a first terminal and a second terminal, said first terminal of said diode being coupled to said first voltage terminal of said voltage converter, said second terminal of said diode being coupled to a first terminal of said resistor, a current flowing from said first terminal of said diode to said second terminal of said diode.

14. The circuit of claim 12 , further comprising a diode having a first terminal and a second terminal, said first terminal of said diode being coupled to said first voltage terminal of said voltage converter, said second terminal of said diode being coupled to a first terminal of said resistor, a current flowing from said second terminal of said diode to said first terminal of said diode.

15. The circuit of claim 12 , wherein said resistor ranges from 100 k-10 M Ohm.

16. The circuit of claim 12 , wherein said first voltage terminal of the voltage converter is a high voltage terminal and said second voltage terminal of the voltage converter is a low voltage terminal.